Journal of Signal Processing Systems

, Volume 70, Issue 2, pp 105–123 | Cite as

Full-Hardware Architectures for Data-Dependent Superimposed Training Channel Estimation

  • Eduardo Romero-Aguirre
  • Roberto Carrasco-Alvarez
  • Ramón Parra-Michel
  • Aldo G. Orozco-Lugo
  • Antonio F. Mondragón-Torres


Channel estimation based on superimposed training (ST) has been an active research topic around the world in recent years, because it offers similar performance when compared to methods based on pilot assisted transmissions (PAT), with the advantage of a better bandwidth utilization. However, physical implementations of such estimators are still under research, and only few approaches have been reported to date. This is due to the computational burden and complexity involved in the algorithms in conjunction with their relative novelty. In order to determine the suitability of the ST-based channel estimation for commercial applications, the performance and complexity analysis of the ST approaches is mandatory. This work proposes two full-hardware channel estimator architectures for a data-dependent superimposed training (DDST) receiver with perfect synchronization and nonexistent DC-offset. These architectures were described using Verilog HDL and targeted in Xilinx Virtex-5 XC5VLX110T FPGA. The synthesis results of such estimators showed a consumption of 3 % and 1 % of total slices available in the FPGA and frequencies operation over 160 MHz. They have also been implemented on a generic 90 nm CMOS process achieving clock frequencies of 187 MHz and 247 MHz while consuming 3.7 mW and 2.74 mW, respectively. In addition, for the first time, a novel architecture that includes channel estimation, training/block synchronization and DC-offset estimation is also proposed. Its fixed-point analysis has been carried out, allowing the design to produce practically equal performance to those achieved with the floating-point models. Finally, the high throughputs and reduced hardware consumptions of the implemented channel estimators, leads to the conclusion that ST/DDST can be utilized in practical communications systems.


Channel estimation Data-dependent superimposed training FPGA architectures  Implicit training Synchronization VLSI 


  1. 1.
    Alameda-Hernandez, E., McLernon, D., Orozco-Lugo, A., Ghogho, M. (2005). Synchronisation and dc-offset estimation for channel estimation using data-dependent superimposed training. In European Signal Processing Conference (EUSIPCO 2005).Google Scholar
  2. 2.
    Alameda-Hernandez, E., McLernon, D., Orozco-Lugo, A., Lara, M., Ghogho, M. (2007). Frame/training sequence synchronization and dc-offset removal for (data-dependent) superimposed training based channel estimation. IEEE Transactions on Signal Processing, 55(6), 2557–2569.MathSciNetCrossRefGoogle Scholar
  3. 3.
    Martín del Campo-Ramírez, F. (2008). Data-dependent superimposed training architecture for wireless communication systems. Master’s thesis, INAOE.Google Scholar
  4. 4.
    Carrasco-Alvarez, R., Parra-Michel, R., Orozco-Lugo, A.G., Tugnait, J.K. (2009). Enhanced channel estimation using superimposed training based on universal basis expansion. IEEE Transactions on Signal Processing, 57(3), 1217– 1222.CrossRefGoogle Scholar
  5. 5.
    Farhang-Boroujeny, B. (1995). Pilot-based channel identification: proposal for semi-blind identification of communication channels. Electronics Letters, 31(13), 1044–1046.CrossRefGoogle Scholar
  6. 6.
    Ghogho, M., McLernon, D., Alameda-Hernandez, E., Swami, A. (2005). Channel estimation and symbol detection for block transmission using data-dependent superimposed training. IEEE Signal Processing Letters, 12(3), 226– 229.CrossRefGoogle Scholar
  7. 7.
    Ghogho, M., & Swami, A. (2004). Improved channel estimation using superimposed training. In Proc. IEEE 5th workshop on signal processing advances in wireless communications (pp. 110–114).Google Scholar
  8. 8.
    Goljahani, A., Benvenuto, N., Tomasin, S., Vangelista, L. (2009). Superimposed sequence versus pilot aided channel estimations for next generation dvb-t systems. IEEE Transactions on Broadcasting, 55(1), 140–144.CrossRefGoogle Scholar
  9. 9.
    Haykin, S., & Ray Liu, K. (2009). Handbook on array processing and sensor networks. Wiley.Google Scholar
  10. 10.
    Kung, S. (1985).VLSI array processors. Prentice Hall.Google Scholar
  11. 11.
    Kuon, I., & Rose, J. (2007), Measuring the gap between fpgas and asics. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 26(2), 203–215.CrossRefGoogle Scholar
  12. 12.
    Longoria-Gandara, O., Parra-Michel, R., Bazdresch, M., Orozco-Lugo, A. (2008). Iterative mean removal superimposed training for SISO and MIMO channel estimation. International Journal of Digital Multimedia Broadcasting, vol. 2008, Article ID 535269, 9 pages, 2008. doi:10.1155/2008/535269.
  13. 13.
    Moldovan, D. (1993). Parallel processing from applications to systems. Morgan Kaufman Publishers, Inc.Google Scholar
  14. 14.
    Najera-Bello, V. (2008). Design and construction of a digital communications system based on implicit training. Master’s thesis, CINVESTAV-IPN.Google Scholar
  15. 15.
    Orozco-Lugo, A., Lara, M., McLernon, D. (2004) Channel estimation using implicit training. IEEE Transactions on Signal Processing, 52(1), 240–254.MathSciNetCrossRefGoogle Scholar
  16. 16.
    Romero-Aguirre, E., Parra-Michel, R., Carrasco-Alvarez, R., Orozco-Lugo, A. (2011). Architecture based on array processors for data-dependent superimposed training channel estimation. In 2011 international conference on, reconfigurable computing and FPGAs (ReConFig) (pp. 303–308).Google Scholar
  17. 17.
    Romero-Aguirre, E., Parra-Michel, R., Orozco-Lugo, A.G., Carrasco-Alvarez, R. (2011). Full-hardware architectures for data-dependent superimposed training channel estimation. In SiPS (pp. 49–54).Google Scholar
  18. 18.
    Tugnait, J., & Luo, W. (2003). On channel estimation using superimposed training and first-order statistics. In Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP ’03) (Vol. 4, pp. IV–624–7).Google Scholar
  19. 19.
    Tugnait, J., & Meng, X. (2006). On superimposed training for channel estimation: performance analysis, training power allocation, and frame synchronization. IEEE Transactions on Signal Processing, 54(2), 752–765.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2012

Authors and Affiliations

  • Eduardo Romero-Aguirre
    • 1
  • Roberto Carrasco-Alvarez
    • 2
  • Ramón Parra-Michel
    • 1
  • Aldo G. Orozco-Lugo
    • 3
  • Antonio F. Mondragón-Torres
    • 4
  1. 1.Department of Electrical EngineeringCIVESTAV-GDLZapopanMéxico
  2. 2.Department of Electronic EngineeringUDG-CUCEIGuadalajaraMéxico
  3. 3.Department of Electrical EngineeringCINVESTAV-DFMéxicoMéxico
  4. 4.Department of Electrical, Computer and Telecommunications Engineering TechnologyRITRochesterUSA

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