High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator
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Mersenne Twister (MT) uniform random number generators are key cores for hardware acceleration of Monte Carlo simulations. In this work, two different architectures are studied: besides the classical table-based architecture, a different architecture based on a circular buffer and especially targeting FPGAs is proposed. A 30% performance improvement has been obtained when compared to the fastest previous work. The applicability of the proposed MT architectures has been proven in a high performance Gaussian RNG.
KeywordsMersenne-Twister URNG FPGA Monte Carlo
This work has been funded by BBVA contract P060920579 and Cicyt project TEC2009-08589.
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