Journal of Signal Processing Systems

, Volume 69, Issue 3, pp 293–304 | Cite as

A Reconfigurable TDMP Decoder for Raptor Codes

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Abstract

A Raptor code is a concatenation of a fixed rate precode and a Luby-Transform (LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized by irregularity features such as dynamic rate, check-degree variability, and joint coding, which make the design of hardware-efficient decoders a challenging task. In this paper, serial turbo decoding of architecture-aware Raptor codes is mapped into sequential row processing of a regular matrix by using a combination of code enhancements and architectural optimizations. The proposed mapping approach is based on three basic steps: (1) applying systematic permutations on the source matrix of the Raptor code, (2) confining LT random encoding to pseudo-random permutation of messages and periodic selection of row-splitting scenarios, and (3) developing a reconfigurable parallel check-node processor that attains a constant throughput while processing LT- and LDPC-nodes of varying degrees and count. The decoder scheduling is, thus, made simple and uniform across both LDPC and LT decoding. A serial decoder implementing the proposed approach was synthesized in 65 nm, 1.2 V CMOS technology. Hardware simulations show that the decoder, decoding a rate-0.4 code instance, achieves a throughput of 36 Mb/s at SNR of 1.5 dB, dissipates an average power of 27 mW and occupies an area of 0.55 mm2.

Keywords

Raptor codes Reconfigurable decoder Error-correcting code Decoder architecture 
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Notes

Acknowledgements

We would like to thank Professor Fadi Kurdahi and Mr. Xiaoliang Chen, from the University of California, Irvine, for their vital help in the synthesis of the decoder.

References

  1. 1.
    Design Compiler. http://www.synopsys.com.
  2. 2.
    Elias, P. (1955). Coding for two noisy channels. In Third London symposium on information theory (pp. 61–76).Google Scholar
  3. 3.
    Etesami, O., & Shokrollahi, A. (2006). Raptor codes on binary memoryless symmetric channels. IEEE Transactions on Information Theory, 52(5), 2033–2051.MathSciNetCrossRefGoogle Scholar
  4. 4.
    Fossorier, M., Mihaljevic, M., & Imai, H. (1999). Reduced complexity iterative decoding of low-density parity-check codes based on belief propagation. IEEE Transactions on Communications, 47(5), 673–680.CrossRefGoogle Scholar
  5. 5.
    Gallager, R. G. (1963). Low-density parity-check codes. Cambridge: MIT Press.Google Scholar
  6. 6.
    Kai Zhang, X. H., & Wang, Z. (2009). High-throughput layered decoder implementation for quasi-cyclic ldpc codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(6), 985–994.Google Scholar
  7. 7.
    Luby, M. (2002). LT-codes. In Proc. the 43rd annual IEEE symposium on the foundations of computer science (pp. 271–280). Vancouver, BC, Canada.Google Scholar
  8. 8.
    Mansour, M. M. (2006). A turbo-decoding message-passing algorithm for sparse parity-check matrix codes. IEEE Transactions on Signal Processing, 54(11), 4376–4392.MathSciNetCrossRefGoogle Scholar
  9. 9.
    Mansour, M. M., & Shanbhag, N. R. (2003). High-throughput LDPC decoders. IEEE Transactions on VLSI Systems, 11(6), 976–996.CrossRefGoogle Scholar
  10. 10.
    Palanki, R., & Yedidia, J. S. (2004). Rateless codes on noisy channels. In Proc. int. symposium on info (p. 37). Theory, Chicago, Illinois USA.Google Scholar
  11. 11.
    Shokrollahi, A. (2006). Raptor codes. IEEE Transactions on Information Theory, 52(6), 2551–2567.MathSciNetCrossRefGoogle Scholar
  12. 12.
    Tanner, R. M. (1981). A recursive approach to low complexity codes. IEEE Transactions on Information Theory, IT-27, 533–547.MathSciNetCrossRefGoogle Scholar
  13. 13.
    Xiang, B., Shen, R., Pan, A., Bao, D., & Zeng X. (2010). An area-efficient and low-power multirate decoder for quasi-cyclic low-density parity-check codes. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 18(10), 1447–1460.CrossRefGoogle Scholar
  14. 14.
    Zeineddine, H., Mansour, M., & Puri, R. (2011). Construction and hardware-efficient decoding of raptor codes. IEEE Transactions on Signal Processing, 59(6), 2943–2960.MathSciNetCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  1. 1.American University of BeirutBeirutLebanon

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