Design Methodology for Offloading Software Executions to FPGA

  • Tomasz Patyk
  • Perttu Salmela
  • Teemu Pitkänen
  • Pekka Jääskeläinen
  • Jarmo Takala
Article

Abstract

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload computations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and application-specific requirements.

Keywords

Application-specific integrated circuits Hardware accelerator Computer aided engineering System-on-a-chip Coprocessors Field programmable gate arrays 

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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Tomasz Patyk
    • 1
  • Perttu Salmela
    • 1
  • Teemu Pitkänen
    • 1
  • Pekka Jääskeläinen
    • 1
  • Jarmo Takala
    • 1
  1. 1.Department of Computer SystemsTampere University of TechnologyTampereFinland

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