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Journal of Signal Processing Systems

, Volume 64, Issue 1, pp 149–159 | Cite as

Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU

  • Hyunwoo JiEmail author
  • Junho Cho
  • Wonyong Sung
Article

Abstract

Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.

Keywords

Low-density parity-check (LDPC) codes Compute Unified Device Architecture (CUDA) General Purpose Graphics Processing Unit (GPGPU) Memory access optimization 

Notes

Acknowledgements

This work was supported in part by the National Research Foundation (NRF) grant funded by the Korea government (MEST) (No. 20090075770 and No. 20090084804) and in part by the MEST under the Brain Korea 21 Project.

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Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.School of Electrical EngineeringSeoul National UniversitySeoulSouth Korea

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