Journal of Signal Processing Systems

, Volume 66, Issue 1, pp 25–41 | Cite as

Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support

  • Rizwan Asghar
  • Di Wu
  • Ali Saeed
  • Yulin Huang
  • Dake Liu
Article

Abstract

This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm2 area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm2/Mbps and energy efficiency of 0.55 nJ/b/iter.

Keywords

Turbo codes VLSI implementation Radix-4 Parallel interleaver Multimode 

Notes

Acknowledgment

This work is supported in part by the Multi-base Project from European Commission’s 7th Framework in partner with Ericson AB, Infineon Austria AG, IMEC, Lund University and KU-Leuven.

References

  1. 1.
    3GPP (2008). Technical Specification Group Radio Access Network; Multiplexing and Channel Coding (FDD) (25.212 V8.4.0). Dec.Google Scholar
  2. 2.
    DVB-SH (2008). Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for satellite services to handheld devices (SH) below 3 GHz. ETSI EN 302–583 V1.1.1, March.Google Scholar
  3. 3.
    3GPP-LTE. Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and Channel Coding. Release 8, 3GPP TS 36.212 v8.0.0, (2007–09).Google Scholar
  4. 4.
    IEEE 802.16e–2005 (2005). IEEE Standard for Local and Metropolitan Area Networks, Part 16: Air interface for fixed broadband wireless access systems—amendment 2: medium access control layers for combined fixed and mobile operations in licensed bands.Google Scholar
  5. 5.
    Bougard, B., et al. (2003). A scalable 8.7 nJ/bit 75.6 Mb/s parallel concatenated convolutional (turbo-) codec. IEEE International Solid-State Circuits Conference (ISSCC), pp. 152–153, vol. 1, Feb.Google Scholar
  6. 6.
    Thomas, C., et al. (2003). Integrated circuits for channel coding in 3G cellular mobile wireless systems. IEEE Communications Magazine, 41(8), 150–159.CrossRefGoogle Scholar
  7. 7.
    Lin, C.-H., Chen, C.-Y., & Wu, A.-Y. (2008). High-throughput 12-mode CTC decoder for WiMAX standard. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 216–219, April.Google Scholar
  8. 8.
    Prescher, G., Gemmeke, T., & Noll, T. G. (2005). A parametrizable low-power high throughput turbo decoder. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 25–28, March.Google Scholar
  9. 9.
    Kim, J. H., & Park, I. C. (2008). Duo-binary circular turbo decoder based on border metric encoding for WiMAX. Asia and South Pacific Design Automation Conference (ASPDAC), pp. 109–110, March.Google Scholar
  10. 10.
    Wang, Z., & Parhi, K. K. (2003). High performance, high throughput turbo/SOVA decoder design. IEEE Transactions on Communications, 51(4), 570–579.CrossRefGoogle Scholar
  11. 11.
    Yoon, S., & Bar-Ness, Y. (2002). A parallel MAP algorithm for low latency turbo decoding. IEEE Communication Letters, 6, 288–290.CrossRefGoogle Scholar
  12. 12.
    Dingninou, A., Raouafi, F., & Berrou, C. (1999). Organisation de la memoire dans un turbo decodeur utilisant l’algorithm SUB-MAP. Proceedings of GRETSI, pp. 71–74, France, Sept.Google Scholar
  13. 13.
    Bickerstaff, M., Davis, L., Thomas, C., Garret, D., & Nicol, C. (2003). A 24 Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless. IEEE International Solid-State Circuits Conference (ISSCC), pp. 150–151, vol. 1, Feb.Google Scholar
  14. 14.
    Shin, M., & Park, I.-C. (2007). SIMD processor-based turbo decoder supporting multiple third-generation wireless standards. IEEE Transactions on VLSI, 15(7), 801–810.CrossRefGoogle Scholar
  15. 15.
    Asghar, R., Wu, D., Eilert, J., & Liu, D. (2010). Memory conflict analysis and implementation of a re-configurable interleaver architecture supporting unified parallel turbo decoding. Journal of Signal Processing Systems, 60(1), July. doi: 10.1007/s11265-009-0394-8.
  16. 16.
    Zhan, C., Arslan, T., Erdogan, A. T., & MacDougall, S. (2006). An efficient decoder scheme for double binary circular turbo codes. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp. 229–232, May.Google Scholar
  17. 17.
    Sun, Y., Zhu, Y., Goel, M., & Cavallaro, J. R. (2008). Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 209–214, July.Google Scholar
  18. 18.
    Papaharalabos, S., Sweeny, P., & Evans, B. G. (2006). Constant log-map decoding algorithm for duo-binary turbo code. IEEE Electronic Letters, 42(12), 709–710.CrossRefGoogle Scholar
  19. 19.
    Thul, M. J., Gilbert, R., Vogt, T., Kreiselmaier, G., & When, N. (2005). A scalable system architecture for high-throughput turbo-decoders. Journal of VLSI Signal Processing, 39, 63–77.MATHCrossRefGoogle Scholar
  20. 20.
    Lee, S. J., Sanbhag, N. R., & Singer, A. C. (2005). A 285 MHz pipelined MAP decoder in 0.18 μm CMOS. IEEE Journal of Solid-State Circuits (JSSC), 40(8), 1718–1725.CrossRefGoogle Scholar
  21. 21.
    Kim, J. H., & Park, I. C. (2008). A 50 Mbps double-binary turbo decoder for WiMAX based on bit-level extrinsic information exchange. IEEE Asian Solid-State Circuits Conference (ASSCC), pp. 305–308, Nov.Google Scholar
  22. 22.
    Benkeser, C., Burg, A., Cupaiuolo, T., & Huang, Q. (2009). Design and optimization of an HSDPA turbo decoder ASIC. IEEE Journal of Solid-State Circuits (JSSC), 44(1), 98–106.CrossRefGoogle Scholar
  23. 23.
    Wong, C. C. et al. (2007). A 0.22 nJ/b/iter 0.13 μm turbo decoder chip using inter-block permutation interleaver. IEEE Custom Integrated Circuits Conference (CICC), pp. 273–276, Sept.Google Scholar
  24. 24.
    Robertson, P., Hoeher, P., & Villebrun, E. (1997). Optimal and sub-optimal maximum a posteriori algorithms suitable for turbo decoding. European Transaction on Telecommunication, 8(2), 119–125.CrossRefGoogle Scholar
  25. 25.
    Pietrobon, S. (1998). Implementation and performance of turbo/MAP decoder. International Journal of Satellite Communication, 15, 23–46.CrossRefGoogle Scholar
  26. 26.
    Robertson, P., Villeburn, E., & Hoeher, P. (1995). A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain. IEEE International Conference on Communications (ICC), pp. 1009–1013, June.Google Scholar
  27. 27.
    Wang, Z., Tang, Y., & Wang, Y. (2003). Low hardware complexity parallel turbo decoder architecture. IEEE International Symposium on Circuits and System (ISCAS), pp. 53–56, May.Google Scholar
  28. 28.
    Takeshita, O. Y., & Costello, D. J., Jr. (2000). New deterministic interleaver designs for turbo codes. IEEE Transaction for Information Theory, 46(6), 1988–2006.MATHCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Rizwan Asghar
    • 1
  • Di Wu
    • 1
  • Ali Saeed
    • 1
  • Yulin Huang
    • 1
  • Dake Liu
    • 1
  1. 1.Department of Electrical EngineeringLinköping UniversityLinköpingSweden

Personalised recommendations