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An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV

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Abstract

Fractional Motion Estimation (FME) in high-definition H.264 presents a significant design challenge in terms of memory bandwidth, latency and area cost as there are various modes and complex mode decision flow, which require over 45% of the computation complexity in the H.264 encoding process. In this paper, a new high-performance VLSI architecture for Fractional Motion Estimation (FME) in H.264/AVC based on the full-search algorithm is presented. This architecture is made up of three different pipeline processors to establish a trade-off between processing time and hardware utilization. The computing scheme based on a 4-pixel interpolation unit with a 10-pixel input bandwidth is capable of processing a macroblock (MB) in 870 clock cycles. The final VLSI implementation only requires 11.4 k gates and 4.4kBytes of RAM in a standard 180 nm CMOS technology operating at 290 MHz. Our design generates the residual image and the best MVs and mode in a high throughput and low area cost architecture while achieving enough processing capacity for 1080HD (1920 × 1088@30fps) real-time video streams.

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Acknowledgment

We wish to acknowledge the Spanish Ministry of Education and Science for the financial help TEC2006-12438/TCM received to support this work.

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Correspondence to G. A. Ruiz.

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Ruiz, G.A., Michell, J.A. An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV. J Sign Process Syst 62, 443–457 (2011). https://doi.org/10.1007/s11265-010-0475-8

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Keywords

  • H.264
  • High-definition television (HDTV)
  • Fractional motion estimation
  • Video coding