Journal of Signal Processing Systems

, Volume 62, Issue 3, pp 341–357 | Cite as

Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis

  • Bertrand Le GalEmail author
  • Emmanuel Casseau


Multimedia applications such as video and image processing are often characterized as computation intensive applications. For these applications the word-length of data and instructions is different throughout the application. Generating hardware architectures is not a straightforward task since it requires a deep word-length analysis in order to properly determine what hardware resources are needed. In this paper we suggest an automated design methodology based on high-level synthesis which takes care of data word-length and interconnection resource cost in order to generate area and power efficient fixed-point architectures for DSP applications. Both ASIC and FPGA technologies are targeted. Experimental results show that our proposed approach reduces area by 6% to 42% on FPGA technology and by 9% to 48 % on ASIC compared to previous approaches. Power saving can reach up to 44% on FPGA technology and 36% on ASIC.


Data sizing Hardware design High-level synthesis Resource sharing 


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© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.IMS Laboratory, CNRS - UMR 5218Bordeaux Polytechnic Institute, University of BordeauxTalenceFrance
  2. 2.French National Institute for Research in Computer Science and ControlINRIA/IRISALannionFrance

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