A programmable instruction decoder (PID) is introduced for designing adaptive multi-core DSP architectures by using a hardware/software co-reconfigurable approach without employing programmable devices. This PID permits DSP software developers for post-manufacturing modification of their DSP instruction sets to add their application-specific instructions whenever necessary. In addition, PID offers software developers an enhanced means to utilize the underlying DSP architectures by rescheduling implemented micro-operations for their tailored instructions in the DSP processors. Thus, emerging DSP applications can be swiftly and efficiently re-imported to PID-based DSP processors without re-fabrication of new DSP chips. In addition to instruction-level modification, an innovative instruction-packing procedure for PID is presented for further enhancement of the PID-based DSP systems. PID architecture was developed and implemented in VHDL. The PID-based DSP systems were also developed and evaluated to demonstrate various post-manufacturing adaptabilities in DSP processor systems. Various multi-core DSP architectures based on Texas Instruments’ TMS320C55 DSP processor were used for evaluating performance and adaptability of this new programmable instruction decoder.
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Jung, Y. Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures. J Sign Process Syst 62, 273–285 (2011). https://doi.org/10.1007/s11265-010-0461-1
- Programmable DSP
- Instruction set extension
- Instruction packing
- Hardware/software co-reconfiguration
- Programmable instruction decoder
- Adaptive computer
- Multi-processor SoC (MPSoC)