Journal of Signal Processing Systems

, Volume 60, Issue 1, pp 15–29 | Cite as

Memory Conflict Analysis and Implementation of a Re-configurable Interleaver Architecture Supporting Unified Parallel Turbo Decoding



This paper presents a novel hardware interleaver architecture for unified parallel turbo decoding. The architecture is fully re-configurable among multiple standards like HSPA Evolution, DVB-SH, 3GPP-LTE and WiMAX. Turbo codes being widely used for error correction in today’s consumer electronics are prone to introduce higher latency due to bigger block sizes and multiple iterations. Many parallel turbo decoding architectures have recently been proposed to enhance the channel throughput but the interleaving algorithms used in different standards do not freely allow using them due to higher percentage of memory conflicts. The architecture presented in this paper provides a re-configurable platform for implementing the parallel interleavers for different standards by managing the conflicts involved in each. The memory conflicts are managed by applying different approaches like stream misalignment, memory division and use of small FIFO buffer. The proposed flexible architecture is low cost and consumes 0.085 mm2 area in 65 nm CMOS process. It can implement up to 8 parallel interleavers and can operate at a frequency of 200 MHz, thus providing significant support to higher throughput systems based on parallel SISO processors.


Parallel interleaver Parallel turbo decoding Block interleaver Multi standard HSPA LTE WiMAX DVB-SH 


  1. 1.
    Berrou, C., Glavieus, A., & Thitimajshima, P. (1993). Near Shannon limit error-correcting coding and decoding: Turbo-codes. Proceedings of IEEE ICC, 2, 1064–1070.CrossRefGoogle Scholar
  2. 2.
    3GPP, (2004). Technical specification group radio access network; multiplexing and channel coding (FDD) (25.212 V5.9.0). June 2004.Google Scholar
  3. 3.
    3GPP, (2008). Technical specification group radio access network; multiplexing and channel coding (FDD) (25.212 V8.4.0). Dec. 2008.Google Scholar
  4. 4.
    ETSI EN 302-583 V1.1.1, (2008). Digital Video Broadcasting (DVB); Framing structure, channel coding and modulation for satellite services to handheld devices (SH) below 3 GHz. March. 2008.Google Scholar
  5. 5.
    3GPP-LTE, (2007). Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA); multiplexing and channel coding. Release 8, 3GPP TS 36.212 v8.0.0, (2007–09).Google Scholar
  6. 6.
    IEEE 802.16e–2005, “IEEE Standard for Local and Metropolitan Area Networks, Part 16: Air Interface for Fixed Broadband Wireless Access Systems—Amendment 2: Medium Access Control Layers for Combined Fixed and Mobile Operations in Licensed Bands”.Google Scholar
  7. 7.
    Zhang, Y., & Parhi, K. K., (2004). Parallel turbo decoding, vol. 2, (pp. II-509–512). Proceedings of ISCAS, May 2004.Google Scholar
  8. 8.
    Lu, Y. C., & Lu, E. H, (2007). A parallel decoder design for low latency turbo decoding (pp. 386–389). Proceedings of ICICIC.Google Scholar
  9. 9.
    Sun, Y., Zhu, Y., Goel, M., & Cavallaro, J. R. (2008). Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards (pp. 209–214). Proceedings of ASAP 2008.Google Scholar
  10. 10.
    Lin, C.-H., Chen, C.-Y., Wu, A.-Y, (2008). High-Throughput 12-Mode CTC Decoder for WiMAX Standard (pp. 216–219). Proceedings of IEEE VLSI-DAT, April 2008.Google Scholar
  11. 11.
    Dobkin, R., Peleg, M., & Ginosar, R. (2005). Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Transaction on VLSI Systems, 13(4), 427–438.CrossRefGoogle Scholar
  12. 12.
    Giulietti, A., van der Perre, L., & Strum, M. (2002). Parallel turbo coding interleavers: avoiding collisions in accesses to storage elements. IEE Electronic Letters, 38(5), 232–234.CrossRefGoogle Scholar
  13. 13.
    Kwak, J., Park, S-M., Yoon S-S., & Lee, K. (2003). Implementation of a parallel turbo decoder with dividable interleaver, vol. 2 (pp. 65–68). Proceedings of ISCAS, May 2003.Google Scholar
  14. 14.
    Shin, M., & Park, I.-C. (2003). Processor-based turbo interleaver for multiple third-generation wireless standards. IEEE Communication Letters, 7(5), 210–212.CrossRefGoogle Scholar
  15. 15.
    Ampadu, P., & Kornegay, K. (2003) An efficient hardware interleaver for 3G turbo decoding (pp. 199–201). RAWCON, August 2003.Google Scholar
  16. 16.
    Asghar, R., & Liu, D. (2008). Very low cost configurable hardware interleaver for 3G turbo decoding (pp. 1–5). Proceedings of ICTTA, April 2008.Google Scholar
  17. 17.
    Asghar, R., & Liu, D. (2008). Dual standard re-configurable hardware interleaver for turbo decoding (pp. 768–772). Proceedings of ISWPC, May 2008.Google Scholar
  18. 18.
    Wang, Z., & Li, Q. (2007). Very low-complexity hardware interleaver for turbo decoding. IEEE Transaction on Circuits and System—II, 54(7), 636–640.CrossRefGoogle Scholar
  19. 19.
    Asghar, R., & Liu, D. (2009). Low complexity multi mode interleaver core for WiMAX with support for convolutional interleaving. Journal of Electronics Communications and Computer Engineering, 3(1), 20–29.Google Scholar
  20. 20.
    Blakley, G. R. (1983). A computer algorithm for calculating the product A*B mod M. IEEE Transaction on Computers, C-32(5), 497–500.CrossRefGoogle Scholar
  21. 21.
    Asghar, R., Wu, D., Eilert, J., & Liu, D. (2009) Memory conflict analysis and interleaver design for parallel turbo decoding supporting HSPA evolution. Accepted for publication in 12th Euromicro DSD-2009, August 2009.Google Scholar
  22. 22.
    Speziali, F., & Zory, J. (2004). Scalable and area efficient concurrent interleaver for high throughput turbo-decoders (pp. 334–341). Proceedings of Euromicro DSD-2004.Google Scholar
  23. 23.
    Martna, M., Nicola, M., & Masera, G. (2008). Hardware design of a low complexity, parallel interleaver for WiMAX Duo-Binary turbo decoding. IEEE Communication Letters, 12(11), 846–848.CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Department of Electrical EngineeringLinköping UniversityLinköpingSweden

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