Journal of Signal Processing Systems

, Volume 58, Issue 3, pp 301–310 | Cite as

Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA

  • Dimitris Bariamis
  • Dimitris MaroulisEmail author
  • Dimitris K. Iakovidis


This paper presents ALA (Adaptable Logarithm Approximation), a novel hardware architecture for the approximation of the base-2 logarithm of integers at an arbitrary accuracy, suitable for fast and area-efficient FPGA implementation. It is based on a piecewise linear approximation methodology, implemented so that an arbitrary number of linear segments approximate the logarithm function. The achieved approximation accuracy depends on the number of segments used, which also affects the size of a ROM used for storing the parameters that control the computation. The implementation of the ROM using an FPGA BlockRAM allows the parameters to be updated without reconfiguration of the FPGA core. This provides the considerable advantage of data set adaptability to the proposed architecture over the other relevant architectures, as the parameters can be easily updated to minimize the approximation error for different data sets. Both real and synthetic datasets have been used for evaluation purposes. The results show that ALA adapts well to all data sets used and requires significantly less FPGA slices than the CORDIC architecture to achieve the same or higher approximation accuracy. Moreover, it provides a throughput of one result per cycle and up to four times lower latency than the CORDIC core.


Field programmable gate arrays Digital design 



This work was realized under the framework of the Reinforcement Program of Human Research Manpower (“PENED 2003”—03ED324), co-funded by the General Secretariat for Research and Technology, Greece, and the European Social Fund.


  1. 1.
    Bariamis, D., Iakovidis, D. K., Maroulis, D. (2006) Dedicated hardware for real-time computation of second-order statistical features for high resolution images. Lecture Notes in Computer Science, Volume 4179 LNCS, pp. 67-77.Google Scholar
  2. 2.
    Karkanis, S. A., Iakovidis, D. K., Maroulis, D. E., Karras, D. A., & Tzivras, M. (2003). Computer aided tumor detection in endoscopic video using color wavelet features. IEEE Trans. Inf. Technol. Biomed., 7, 141–152. doi: 10.1109/TITB.2003.813794.CrossRefGoogle Scholar
  3. 3.
    Nakamura, K. (2002). Development of real-time endoscopic image processing technology: Adaptive index of hemoglobin color enhancement processing. Dig. Endosc, 14(Suppl), S40–S47. doi: 10.1046/j.1443-1661.14.s1.12.x.CrossRefGoogle Scholar
  4. 4.
    Rocke, D. M., & Durbin, B. (2003). Approximate variance-stabilizing transformations for gene-expression microarray data. Bioinformatics, 19(8), 966–972. doi: 10.1093/bioinformatics/btg107.CrossRefGoogle Scholar
  5. 5.
    Mandelbaum, D. M., & Mandelbaum, S. G. (1996). A fast, efficient parallel-acting method of generating functions defined by power series, including logarithm, exponential, and sine. Cosine. IEEE Trans. Parallel Distrib. Syst, 7(1), 33–45. doi: 10.1109/71.481596.CrossRefMathSciNetGoogle Scholar
  6. 6.
    Detrey, J., de Dinechin, F. (2009) Parametrized floating-point logarithm and exponential functions for FPGA. Microprocessors Microsystems.Google Scholar
  7. 7.
    Pineiro, J.-A., Ercegovac, M. D., Bruguerax, J. D. (2002) High–Radix Logarithm with Selection by Rounding. Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP02, 101–110.Google Scholar
  8. 8.
    Starzyk, J.A., Guo, Y. (2001) An entropy-based learning hardware organization using FPGA, in Proc. Southeastern Symposium on System Theory (pp. 1–5), Athens, OH.Google Scholar
  9. 9.
    Volder, J. E. (1959). The CORDIC trigonometric computing technique. IRE Trans. Electron. Comput, EC-8, 330–334.CrossRefGoogle Scholar
  10. 10.
    Mitchell, J. N., Jr. (1962). Computer multiplication and division using binary logarithms. IRE Trans. Electron. Comput., 11, 512–517.CrossRefGoogle Scholar
  11. 11.
    SanGregory, S. L., Siferd, R. E., Brother, C., Gallagher, D. (1999) A Fast, Low-Power Logarithm Approximation with CMOS VLSI Implementation. Proc. IEEE Midwest Symp. Circuits and Systems.Google Scholar
  12. 12.
    Combet, M., Zonneveld, H., & Verbeek, L. (1965). Computation of the base two logarithm of binary numbers. IEEE Trans. Electron. Comput, 14, 863–867. doi: 10.1109/PGEC.1965.264080.CrossRefGoogle Scholar
  13. 13.
    Hall, E. L., Lynch, D. D., & Dwyer, S. J. I. I. I. (1970). Generation of products and quotients using approximate binary logarithms for digital filtering applications. IEEE Trans. Comput, 19, 97–105. doi: 10.1109/T-C.1970.222874.zbMATHCrossRefGoogle Scholar
  14. 14.
    Abed, K. H., & Siferd, R. E. (2003). CMOS VLSI Implementation of a low-power logarithmic converter. IEEE Trans. Comput, 52, 1421–1433. doi: 10.1109/TC.2003.1244940.CrossRefGoogle Scholar
  15. 15.
    Lang, T., & Antelo, E. (2005). High-throughput CORDIC-based geometry operations for 3D computer graphics. IEEE Trans. Comput, 54(3), 347–361. doi: 10.1109/TC.2005.53.CrossRefGoogle Scholar
  16. 16.
    Metafas, D. E., & Goutis, C. E. (1995). A floating-point advanced cordic processor. J. VLSI Signal Process, 10(1), 53–65. doi: 10.1007/BF02407026.CrossRefGoogle Scholar
  17. 17.
    Walther, J. S. (1971). A unified algorithm for elementary functions. in Proceedings of the 38th Spring Joint Computer Conference (pp. 379–385).Google Scholar
  18. 18.
    Xilinx LogiCORE CORDIC v3.0 Product Specification DS249, Xilinx Inc., 2005Google Scholar
  19. 19.
    Stanford MicroArray Database:

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • Dimitris Bariamis
    • 1
  • Dimitris Maroulis
    • 1
    Email author
  • Dimitris K. Iakovidis
    • 1
  1. 1.Department of Informatics and TelecommunicationsUniversity of AthensAthensGreece

Personalised recommendations