Journal of Signal Processing Systems

, Volume 58, Issue 3, pp 281–299 | Cite as

Fully Systolic FFT Architecture for Giga-sample Applications

  • K. Babionitakis
  • V. A. Chouliaras
  • K. Manolopoulos
  • K. Nakos
  • D. Reisis
  • N. Vlassopoulos
Article

Abstract

We present a novel 4096 complex-point, fully systolic VLSI FFT architecture based on the combination of three consecutive radix-4 stages resulting in a 64-point FFT engine. The outcome of cascading these 64-point FFT engines is an improved architecture that efficiently processes large input data sets in real time. Using 64-point FFT engines reduces the buffering and the latency to one third of a fully unfolded radix-4 architecture, while the radix-4 schema simplifies the calculations within each engine. The proposed 4096 complex point architecture has been implemented on a FPGA achieving a post-route clock frequency of 200 MHz resulting in a sustained throughput of 4096 point/20.48 μs. It has also been implemented on a high performance 0.13 μm, 1P8M CMOS process achieving a worst-case (0.9 V, 125 C) post-route clock frequency of 604.5 MHz and a sustained throughput of 4096 point/3.89 μs while consuming 4.4 W. The architecture is extended to accomplish FFT computations of 16K, 64K and 256K complex points with 352, 256 and 188 MHz operating frequencies respectively.

Keywords

Fast Fourier transform (FFT) VLSI FPGA Radix-2 Radix-4 Real-time processing 

References

  1. 1.
    Ersoy, O. K. (1997). Fourier-related transforms, fast algorithms and applications. Englewood Cliffs: Prentice Hall.MATHGoogle Scholar
  2. 2.
    Thompson, C. D. (1983). Fourier transform in VLSI. IEEE Transactions on Computers, 32, 1047–1057.MATHCrossRefGoogle Scholar
  3. 3.
    Wold, E. H., & Despain, A. M. (1984). Pipeline and parallel FFT processors for VLSI implementations. IEEE Transactions on Computers, C-33, 414-426.CrossRefGoogle Scholar
  4. 4.
    He, S., & Torkelson, M. (1996). A new approach to pipeline FFT processor. In Proceedings of the IPPS.Google Scholar
  5. 5.
    Choi, S., Govindu, G., Jang, J. W., & Prasanna, V. K. (2003). Energy-efficient and parameterized designs of fast fourier transforms on FPGAs. In The 28th international conference on acoustics, speech, and signal processing (ICASSP).Google Scholar
  6. 6.
    Uzun, I. S., Amira, A., & Bouridane, A. (2005). FPGA implementations of fast fourier transforms for real-time signal and image processing. IEEE Vision, Image and Signal Processing, 152, 283–296.CrossRefGoogle Scholar
  7. 7.
    Oppenheim, A., & Schafer, R. (1975). Digital signal processing. Englewood Cliffs: Prentice Hall.MATHGoogle Scholar
  8. 8.
    Lee, J., Lee, J., Sunwoo, M. H., Moh, S., & Oh, S. (2002). A DSP architecture for high-speed FFT in OFDM systems. ETRI Journal, 24, 391–397.CrossRefGoogle Scholar
  9. 9.
    He, S., & Torkelson, M. (1998). Design and implementation of a 1024-point pipeline FFT processor. In IEEE 1998 Custom integrated circuits.Google Scholar
  10. 10.
    Rabiner, L. R., & Gold, B. (1975). Theory and application of digital signal processing. Englewood Cliffs: Prentice-Hall.Google Scholar
  11. 11.
    Suter, B., & Stevens, K. S. (1998). A low power, high performance approach for time-frequency / time-scale computations. In Proceedings SPIE98 conference on advanced signal processing algorithms, architectures and implementations VIII (Vol. 3461, pp. 86–90).Google Scholar
  12. 12.
    Lenart, T., & Owall, V. (2003). A 2048 complex point FFT processor using a novel data scaling approach. In IEEE ISCAS.Google Scholar
  13. 13.
    Cortes, A., Velez, I., Zalbide, I., Irizar, A., & Sevillano, J. F. (2006). An FFT core for DVB-T/DVB-H receivers. In ICECS’06 (pp. 102–105).Google Scholar
  14. 14.
    Maharatna, K., Grass, E., & Jagdhold, U. (2004). A 64-point fourier transform chip for high-speed wireless LAN applications using OFDM. IEEE Journal of Solid-State Circuits, 39(3), 484–493.CrossRefGoogle Scholar
  15. 15.
    Oh, J. Y., & Lim, M. S. (2005). New radix-2 to the 4th power pipeline FFT processor. IEICE Transactions on Electronics, E88-C(8), 1740–1746.CrossRefGoogle Scholar
  16. 16.
    Bouguezel, S., Ahmad, M. O., & Swamy, M. N. S. (2004). A new radix-2/8 FFT algorithm for length− q×2m DFTs. IEEE Transactions on Circuits and Systems I, 51(9), 1723–1732.CrossRefMathSciNetGoogle Scholar
  17. 17.
    Jo, B. G., & Sunwoo, M. H. (2005). New cotinuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy. IEEE Transactions on Circuits and Systems I, 52(5), 911–919.CrossRefMathSciNetGoogle Scholar
  18. 18.
    Bouguezel, S., Ahmad, M. O., & Swamy, M. N. S. (2006). New radix-(2×2×2)/(4×4×4) and radix-(2×2×2)/(8×8×8) DIF FFT algorithms for 3-D DFT. IEEE Transactions on Circuits and Systems I, 53(2), 306—315.CrossRefMathSciNetGoogle Scholar
  19. 19.
    Chang, W. H., & Nguyen, T. (2006). An OFDM-specified lossless FFT architecture. IEEE Transactions on Circuits and Systems I, 53(6), 1235–1243.CrossRefGoogle Scholar
  20. 20.
    Yang, L., Zhang, K., Liu, H., Huang, J., & Huang, S. (2006). An efficient locally pipelined FFT processor. IEEE Transactions on Circuits and Systems II, 53(7), 585–589.CrossRefGoogle Scholar
  21. 21.
    Lin, Y. N., Liu, H. Y., & Lee, C. Y. (2005). A 1-GS/s FFT/IFFT processor for UWB applications. IEEE Journal of SSC, 40(8).Google Scholar
  22. 22.
    Takala, J., & Punkka, K. (2006). Scalable FFT processors and pipelined butterfly units. Journal of VLSI Signal Processing, 43, 113–123.MATHCrossRefGoogle Scholar
  23. 23.
    Wang, S. S., & Li, C. S. (2007). An area-efficient design of variable-length fast Fourier transform processor. Journal of VLSI Signal Processing.Google Scholar
  24. 24.
    Reisis, D., & Vlassopoulos, N. (2006). Address generation techniques for conflict free parallel memory accessing in FFT architectures. In ICECS (1188–1191), December.Google Scholar
  25. 25.
    Bidet, E., Castelain, D., Joanblanq, C., & Stenn, P. (1995). A fast single-chip implementation of 8192 complex point FFT. IEEE Journal of SSC, 30(3), 300–305.Google Scholar
  26. 26.
    Swartzlander, E. E. Jr. (2007). Systolic FFT processors: A personal perspective. Journal of VLSI Signal Processing, 53, 3–14.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • K. Babionitakis
    • 1
  • V. A. Chouliaras
    • 2
  • K. Manolopoulos
    • 1
  • K. Nakos
    • 1
  • D. Reisis
    • 1
  • N. Vlassopoulos
    • 1
  1. 1.Department of Physics, Electronics LaboratoryNational Kapodistrian University of AthensAthensGreece
  2. 2.Department of Electronics and Electrical EngineeringLoughborough UniversityLoughboroughUK

Personalised recommendations