Journal of Signal Processing Systems

, Volume 58, Issue 3, pp 281–299 | Cite as

Fully Systolic FFT Architecture for Giga-sample Applications

  • K. Babionitakis
  • V. A. Chouliaras
  • K. Manolopoulos
  • K. Nakos
  • D. Reisis
  • N. Vlassopoulos


We present a novel 4096 complex-point, fully systolic VLSI FFT architecture based on the combination of three consecutive radix-4 stages resulting in a 64-point FFT engine. The outcome of cascading these 64-point FFT engines is an improved architecture that efficiently processes large input data sets in real time. Using 64-point FFT engines reduces the buffering and the latency to one third of a fully unfolded radix-4 architecture, while the radix-4 schema simplifies the calculations within each engine. The proposed 4096 complex point architecture has been implemented on a FPGA achieving a post-route clock frequency of 200 MHz resulting in a sustained throughput of 4096 point/20.48 μs. It has also been implemented on a high performance 0.13 μm, 1P8M CMOS process achieving a worst-case (0.9 V, 125 C) post-route clock frequency of 604.5 MHz and a sustained throughput of 4096 point/3.89 μs while consuming 4.4 W. The architecture is extended to accomplish FFT computations of 16K, 64K and 256K complex points with 352, 256 and 188 MHz operating frequencies respectively.


Fast Fourier transform (FFT) VLSI FPGA Radix-2 Radix-4 Real-time processing 


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Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  • K. Babionitakis
    • 1
  • V. A. Chouliaras
    • 2
  • K. Manolopoulos
    • 1
  • K. Nakos
    • 1
  • D. Reisis
    • 1
  • N. Vlassopoulos
    • 1
  1. 1.Department of Physics, Electronics LaboratoryNational Kapodistrian University of AthensAthensGreece
  2. 2.Department of Electronics and Electrical EngineeringLoughborough UniversityLoughboroughUK

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