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Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis

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A processor architecture combining high-performance and low-power is presented. A prototype chip, Xetal-II, has been realized in 90 nm CMOS technology based on the proposed architecture. Recent experimental results show a compute performance of up to 140 GOPS at 785 mW when operating at 110 MHz. The main architectural feature that allows high computational efficiency is the massively-parallel single-instruction multiple-data (MP-SIMD) compute paradigm. Due to the high data-level parallelism, applications like video scene analysis can efficiently exploit the proposed architecture. The chip has an internal 16-bit datapath and 10 Mbit of on-chip video memory facilitating energy efficient implementation of video processing kernels.

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Correspondence to Anteneh A. Abbo.

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Abbo, A.A., Kleihorst, R.P. & Schueler, B. Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis. J Sign Process Syst 62, 17–27 (2011). https://doi.org/10.1007/s11265-008-0332-1

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  • Low-power VLSI
  • Parallel processing
  • SIMD
  • Video scene analysis
  • Processor tile
  • Smart cameras