A processor architecture combining high-performance and low-power is presented. A prototype chip, Xetal-II, has been realized in 90 nm CMOS technology based on the proposed architecture. Recent experimental results show a compute performance of up to 140 GOPS at 785 mW when operating at 110 MHz. The main architectural feature that allows high computational efficiency is the massively-parallel single-instruction multiple-data (MP-SIMD) compute paradigm. Due to the high data-level parallelism, applications like video scene analysis can efficiently exploit the proposed architecture. The chip has an internal 16-bit datapath and 10 Mbit of on-chip video memory facilitating energy efficient implementation of video processing kernels.
This is a preview of subscription content, log in to check access.
Buy single article
Instant access to the full article PDF.
Price includes VAT for USA
Subscribe to journal
Immediate online access to all issues from 2019. Subscription will auto renew annually.
This is the net price. Taxes to be calculated in checkout.
Jones, M., & Viola, P. (2003). Fast multi-view face detection. Mitsubishi Electronics Research Laboratory, No. TR2003-96, June.
Lowe, D. G. (2004). Distinctive image features from scale-invariant keypoints. International Journal of Computer Vision, 60(2), 91–110, Nov.
Jonker, P. (1994). Why linear arrays are better image processors. In Proc. 12th IAPR conf. on pattern recognition (pp. 334–338).
Khailany, B., et al. (2001). Imagine: Media processing with streams. In IEEE micro (pp. 35–46), April.
Chen, T., Raghavan, R., Dale, J. N., & Iwata, E. (2007). Cell broadband engine architecture and its first implementation. A performance view. IBM Journal of Research and Development, 51(5), 559–572, Sept.
Kleihorst, R. P., Abbo, A. A., van der Avoird, A., Op de Beeck, M. J. R., Sevat, L., Wielage, P., et al. (2001). Xetal: A low-power high-performance smart camera processor. In ISCAS 2001 (pp. 215–218), May.
Kyo, S., Koga, T., Okazaki, S., & Kuroda, I. (2005). An integrated memory array processor for embedded image recognition systems. In Proc. of ISCA (pp. 134–145), June.
Nakajima, M., et al. (2006). A 40GOPS 250mw massively parallel processor based on matrix architecture. In ISSCC dig. of tech. papers 2006 (pp. 410–411), Feb.
Kondo, T., Kimura, Y., & Sonehara, N. (1993). Single-board simd processors using gate-array lsis for parallel processing. IEICE Transaction on Electronics, vol. E76-C, no. 12, pp. 1827–1834, Dec 1993.
Cheng, C., et al. (2008). An intelligent visual sensor soc with 2790 fps cmos image sensor and 205GOPS/W vision processor. In ISSCC dig. of tech. papers 2008 (pp. 306–307), Feb.
Kim, K., et al. (2008). A 125GOPS 583mW network-on-chip based parallel processor with bio-inspired visual-attention engine. In ISSCC dig. of tech. papers 2008 (pp. 308–309), Feb.
Arakawa, S., et al. (2008). A 512GOPS fully-programmable digital image processor with full hd 1080p processing capabilities. In ISSCC dig. of tech. papers 2008 (pp. 312–313) Feb.
Abbo, A. A., et al. (2008). Xetal-II: A 107GOPS, 600mW massively parallel processor for video scene analysis. IEEE Journal of Solid State Circuits, 43(1), 192–201, January.
Abbo, A. A., & Kleihorst, R. P. (2002). A programmable smart-camera architecture. In ACIVS2002, Gent, Belgium, Sept.
Trimedia Technologies (2008). Trimedia TM-1100. http://www.nxp.com/.
Kleihorst, R., Abbo, A. A., Schueler, B., & Danilin, A. (2007). Camera mote with a high-performance parallel processor for real-time frame-based video processing. In Proceedings of the international conference on distributed camera systems (ICDSC), Sept.
Childers, J., Reinecke, P., Miyaguchi, H., Takahashi, Y., Yaguchi, Y., & Takeyasu, M. (1990). Svp: Serial video processor. In IEEE CICC, 17.3.1.
Blelloch, G. E. (1989). Scans as primitive parallel operations. IEEE Transaction on Computers, 38(11), 1526–1538, Nov.
About this article
Cite this article
Abbo, A.A., Kleihorst, R.P. & Schueler, B. Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis. J Sign Process Syst 62, 17–27 (2011). https://doi.org/10.1007/s11265-008-0332-1
- Low-power VLSI
- Parallel processing
- Video scene analysis
- Processor tile
- Smart cameras