Low-Power Multiplier Design Using a Bypassing Technique
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This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions as well as computations when the horizontally partial product or the vertical operand is zero. Hence, it is a 2-dimensional bypassing method. Thorough post-layout simulations of a 8×8 digital multiplier using the proposed 2-dimensional bypassing method show that the power dissipation of the proposed design is reduced by more than 75% compared to prior designs. Physical measurements on silicon reveal that the proposed digital multiplier saves more than 28% even with pads’ power dissipation compared to the prior works.
KeywordsLow power multiplier Bypassing Partial product Timing control
The authors would like to express their deepest gratefulness to CIC of NSC for their thoughtful chip fabrication service. The authors also like to thank “Aim for Top University Plan” project of NSYSU and MOE, Taiwan, for partially supporting this investigation.
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