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Journal of Signal Processing Systems

, Volume 57, Issue 2, pp 123–137 | Cite as

An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation

  • Yifeng Qiu
  • Wael Badawy
  • Robert Turney
Article

Abstract

A new integrated programmable platform architecture is presented, with the support of multiple accelerators and extensible processing cores. An advanced application for this architecture is to facilitate the implementation of H.264 baseline profile video codec. The platform architecture employs the novel concept of virtual socket and optimized memory access to increase the efficiency for video encoding. The proposed architecture is mapped on an integrated FPGA device, Annapolis WildCard-II™ or WildCard-4™, for verification. According to the evaluation under different configurations, the results show that the overall performance of the architecture, with the integrated accelerators, can sufficiently meet the real-time encoding requirement for H.264 BP at basic levels, and achieve about 2–5.5 and 1–3 dB improvement, in terms of PSNR, as compared with MPEG-2 MP and MPEG-4 SP, respectively. The architecture is highly extensible, and thus can be utilized to benefit the development of multi-standard video codec beyond the description in this paper.

Keywords

H.264/AVC Video codec Architecture Multi-core Accelerator Virtual socket Motion estimation DCT/Q IDCT/Q-1 CAVLC Deblocking 

Notes

Acknowledgement

The authors would like to thank the support from Alberta Informatics Circle of Research Excellence (iCore), Xilinx Inc., Natural Science and Engineering Research Council of Canada (NSERC), Canada Foundation for Innovation (CFI), and the Department of Electrical & Computer Engineering at the University of Calgary.

References

  1. 1.
    Tekalp, M. (1995). Digital video processing. Signal processing series. Upper Saddle River: Prentice Hall, ISBN:0-13-190075-7. August.Google Scholar
  2. 2.
    ISO/IEC (2005). Coding of audio-visual objects—Part 10: Advanced video coding, ISO/IEC 14496-10:2005, December 2005.Google Scholar
  3. 3.
    ISO/IEC (2000). Generic coding of moving pictures and associated audio information: Video, ISO/IEC 13818-2:2000.Google Scholar
  4. 4.
    ITU (2005). Video coding for low bit rate communication, ITU-T recommendation H.263 (01/2005).Google Scholar
  5. 5.
    ISO/IEC (2005). Coding of audio-visual objects—Part 2: Visual, amendment 2: Visual extensions, ISO/IEC 14496-2:2004/Amd.2:2005.Google Scholar
  6. 6.
    Zeidman, B. (2002). Designing with FPGAs and CPLDs. Berkeley: Publishers Group West, ISBN:1-57820-112-8. October.Google Scholar
  7. 7.
    Choi, J., Togawa, N., Yanagisawa, M., Ohtsuki, T. (2003). System architecture based on hardware/software co-design for optimization of video encoders. A white paper.[Online]. www.ohtsuki.comm.waseda.ac.jp/bunken/pdf/2003/2003choi_jinku_itc-cscc2003.pdf, Sept.
  8. 8.
    Badawy, W. (2004). Low power video platforms for mobile applications. Tutorial on IEEE International Symposium on Circuits and Systems, May.Google Scholar
  9. 9.
    Platform-Based Design Solution (2005). CoWare Inc., A white paper. [Online]. www.coware.com/solutions, March.
  10. 10.
    Dehnhardt, A., Kulaczewski, M. B., Pirsch, P., et al. (2005). A multi-core SoC design for advanced image and video compression. 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, 5, v/665–v /668, March.Google Scholar
  11. 11.
    Wiegand, T., Schwarz, H., Joch, A., & Kossentini, F. (2003). Rate-constrained coder control and comparison of video coding standards. IEEE Transactions on Circuits and Systems for Video Technology, 13, 688–703, July.CrossRefGoogle Scholar
  12. 12.
    Ostermann, J., Bormans, J., List, P., et al. (2004). Video coding with H.264/AVC: Tools, performance, and complexity. IEEE Circuits and Systems Magazine, 4, 7–28 First Quarter 2004.CrossRefGoogle Scholar
  13. 13.
    Horowitz, M., Joch, A., Kossentini, F., & Hallapuro, A. (2003). H.264/AVC baseline profile decoder complexity analysis. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 704–716, July.CrossRefGoogle Scholar
  14. 14.
    Saponara, S., Blanch, C., Denolf, K., Bormans, J. (2003). The JVT advanced video coding standard: Complexity and performance analysis on a tool-by-tool basis. In Packet Video Workshop (PV’03), Nantes, France, April.Google Scholar
  15. 15.
    Gupta, P. S., & Ramkishor, K. (2004). Novel algorithm to reduce complexity of quarter pixel motion estimation. Visual Communication and Image Processing (VCIP), Proceedings of SPIE, 5308, 31–36 California, January.Google Scholar
  16. 16.
    Annapolis Micro Systems (2005). WILDCARD™-II and WILDCARD™-4 reference manual, 12968-000 revision 3.2, December.Google Scholar
  17. 17.
    Xilinx Inc. (2006). Virtex-5 platform FPGA family technical backgrounder. A white paper. [Online]. www.xilinx.com/company/press/kits/v5/v5backgrounder.pdf.
  18. 18.
    Amer, I., Badawy, W., & Jullien, G. (2004). Hardware prototyping for The H.264 4 × 4 transformation. Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, 5, 77–80, May.Google Scholar
  19. 19.
    Sayed, M., Amer, I., Badawy, W. (2006). Towards an H.264/AVC full encoder on chip: An efficient real-time VBSME ASIC Chip. In Proceedings of IEEE International Symposium on Circuits and Systems, pp 4, May.Google Scholar
  20. 20.
    Rahman, C. A., & Badawy, W. (2007). A Verilog Model of CAVLC IP-Block for MPEG-4 Part 10, Contribution to AHG on MPEG-4 Part 9: Reference Hardware, ISO/IEC JTC1/SC29/WG11/ M14102, Marrakech, Morocco, January.Google Scholar
  21. 21.
    ISO/IEC (1993). ISO/IEC JTC1/SC29/WG11, MPEG-2 video test model 5 (TM-5), MPEG 1993/N0400, April.Google Scholar
  22. 22.
    ISO/IEC (2001). ISO/IEC JTC1/SC29/WG11, MPEG-4 Video Verification Model Version 18.0 (VM-18), MPEG 2001/N3908, Pisa, Italy.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2008

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of CalgaryAlbertaCanada
  2. 2.DSP Division, MVI GroupXilinx Inc.WatertownUSA

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