Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays


Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering at interior points in the wire. This paper presents a framework for designing and evaluating long, buffered interconnect wires in FPGAs with near-optimal delay performance using HSPICE-derived delays. Given a target physical wire length, width, and spacing, the method determines the number, size, and position of buffers required to obtain the fastest signal velocity for programmable interconnect. While traditional hand-calculations used for ideal repeater placement can be used, they are not very accurate and ignore practical constraints such as the overhead effects of front-end multiplexing and driving logic, “finite” wire length, and a discrete number of repeaters. A metric introduced during the design is the “path delay profile”, or the arrival time of a signal at different points of a long wire. This method is used to design buffering strategies for interconnect based on 0.5, 2, and 3 mm wire lengths in 180 nm technology. These interconnect designs are coded into VPR along with an improved timing analyzer which accurately determines the “path delay profile” arrival times. Using VPR, average critical-path delay is reduced by 19% for 0.5 mm wires and by up to 46% for 3mm wires over previous designs.

This is a preview of subscription content, log in to check access.


  1. 1.

    G. Lemieux, E. Lee, M. Tom, and A. Yu, “Directional and Single-Driver Wiring in FPGA Interconnect,” in International Conference on Field-Programmable Technology, Dec. 2004.

  2. 2.

    M. Lin, A. El Gamal, Y.-C. Lu, and S. Wong, “Performance Benefits of Monolithically Stacked 3D-FPGA,” in International Symposium on FPGAs, Feb. 2006, pp. 113–122.

  3. 3.

    D. Lewis et al, “The Stratix II Logic and Routing Architecture,” in International Symposium on FPGAs, Feb. 2005, pp. 14–20.

  4. 4.

    V. Adler and E. G. Friedman, “Repeater Insertion to Reduce Delay and Power in RC Tree Structures,” in Conference on Signals, Systems & Computers, Nov. 1997, pp. 749–752.

  5. 5.

    V. Adler and E. G. Friedman, “Uniform Repeater Insertion in RC Trees,” IEEE Trans. Circuits Syst. I, vol. 47, no. 10, 2000, pp. 1515–1524.

  6. 6.

    V. Adler and E. G. Friedman, “Repeater Design to Reduce Delay and Power in Resistive Interconnect,” IEEE Trans. Circuits Syst. II, vol. 45, no. 5, 1998, pp. 607–616.

  7. 7.

    C. J. Alpert, J. Hu, S. S. Sapatnekar, and C. N. Sze, “Accurate Estimation of Global Buffer Delay Within a Floorplan,” IEEE Trans. Comput.-Aided Des., vol. 25, no. 6, 2006, pp. 1140–1146.

  8. 8.

    K. Banerjee and A. Mehrotra, “A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs,” IEEE Trans. Electron. Devices, vol. 49, no. 11, 2002, pp. 2001–2007.

  9. 9.

    S. Dhar and M. A. Franklin, “Optimum Buffer Circuits for Driving Long Uniform Lines,” IEEE J. Solid-State Circuits, vol. 26, no. 1, 1991, pp. 32–41.

  10. 10.

    R. H. J. M. Otten, “Global Wires: Harmful?,” in International Symposium on Physical Design, April 1998, pp. 104–109.

  11. 11.

    L. van Ginneken, “Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay,” IEEE International Symposium on Circuits and Systems, May 1990, pp. 865–868.

  12. 12.

    N. Nassif, M. P. Desai, and D. H. Hall, “Robust Elmore Delay models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor,” in Design Automation Conference, 1998, pp. 230–235.

  13. 13.

    V. Betz and J. Rose, “Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect,” in IEEE Custom Integrated Circuits Conference, May 1999, pp. 171–174.

  14. 14.

    V. Betz, J. Rose, and A. Marquardt, Architecture and CAD for Deep-Submicron FPGAs: Kluwer, 1999.

  15. 15.

    G. Lemieux and D. Lewis, Design of Interconnection Networks for Programmable Logic, Kluwer, 2004.

  16. 16.

    G. Lemieux and D. Lewis, “Circuit Design of Routing Switches,” in International Symposium on FPGAs, Feb. 2002, pp. 19–28.

  17. 17.

    S. Sood, M. Greenstreet, and R. Saleh, “A Novel Distributed and Interleaved FIFO for Source-synchronous Interconnect,” VLSI Design and Test Symposium, Goa, India, Aug. 2006.

  18. 18.

    E. Lee, Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays, Masters thesis, Dept. of ECE, University of British Columbia, June 2006.

  19. 19.

    S. Sivaswamy, G. Wang, C. Ababei, K. Bazargan, R. Kastner, and E. Bozorgzadeh, “HARP: Hard-wired Routing Pattern FPGAS,” in International Symposium on FPGAs, February 2005, pp. 21–29.

  20. 20.

    E. Lee, G. Lemieux, S. Mirabbasi, “:Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays,” IEEE International Conference on Field-Programmable Technology, Bangkok, December 2006, pp. 89–96.

Download references

Author information

Correspondence to Guy Lemieux.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Lee, E., Lemieux, G. & Mirabbasi, S. Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays. J Sign Process Syst Sign Image 51, 57–76 (2008).

Download citation


  • FPGA
  • FPGA interconnect
  • interconnect design
  • routing design
  • computer-aided design