Journal of Signal Processing Systems

, Volume 51, Issue 1, pp 123–136 | Cite as

Power Signature Watermarking of IP Cores for FPGAs

Article

Abstract

In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected. In principle, the proposed power watermarking method works for all kinds of FPGAs. For Xilinx FPGAs, we demonstrate in detail that we can integrate the watermarking algorithms and the signature into the functionality of the watermarked core. So it is very hard to remove the watermark without destroying the core. Furthermore, we introduce a detection algorithm which can decode the signature from a voltage trace with high reliability. Additionally, two enhanced robustness algorithms are introduced which improve the detection probability in case of considerable noise sources. Using these techniques, it is possible to decode the signature even if other cores operate on the same device at the same time.

Keywords

watermarking IP cores FPGA power analysis signature IPP 

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References

  1. 1.
    Xilinx, Inc., Next-Generation Virtex Family from Xilinx to Top One Billion Transistor Mark. 03131_nextgen.htm. Available at http://www.xilinx.com/prs_rls/silicon_vir/.
  2. 2.
    L. Boney, A. H. Tewfik, and K. N. Hamdy, “Digital Watermarks for Audio Signals,” in International Conference on Multimedia Computing and Systems, 1996, pp. 473–480. Available at http://citeseer.ist.psu.edu/boney96digital.html.
  3. 3.
    J. Lach, W. H. Mangione-Smith, and M. Potkonjak, “Signature Hiding Techniques for FPGA Intellectual Property Protection,” in Proceedings of ICCAD, 1998, pp. 186–189. Available at http://citeseer.ist.psu.edu/lach98signature.html.
  4. 4.
    Kahng, Lach, Mangione-Smith, Mantik, Markov, Potkonjak, Tucker, Wang, and Wolfe, “Constraint-based Watermarking Techniques for Design IP Protection,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 20, 2001. Available at http://citeseer.ist.psu.edu/kahng01constraintbased.html.
  5. 5.
    D. Kirovski and M. Potkonjak, “Intellectual Property Protection Using Watermarking Partial Scan Chains for Sequential Logic Test Generation,” in Proceedings of ICCAD, 1998. Available at http://citeseer.ist.psu.edu/218548.html.
  6. 6.
    D. Kirovski, Y.-Y. Hwang, M. Potkonjak, and J. Cong, “Intellectual Property Protection by Watermarking Combinational Logic Synthesis Solutions,” in Proceedings of ICCAD, 1998, pp. 194–198. Available at http://citeseer.ist.psu.edu/article/kirovski98intellectual.html.
  7. 7.
    A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe, “Robust IP Watermarking Methodologies for Physical Design,” in Design Automation Conference, 1998, pp. 782–787. Available at http://citeseer.ist.psu.edu/kahng98robust.html.
  8. 8.
    D. Ziener, S. Aßmus, and J. Teich, “Identifying FPGA IP-Cores Based on Lookup Table Content Analysis,” in Proceedings of 16th International Conference on Field Programmable Logic and Applications, Madrid, Spain, Aug. 2006, pp. 481–486.Google Scholar
  9. 9.
    D. Ziener and J. Teich, “Evaluation of Watermarking Methods for FPGA-based IP-cores,” University of Erlangen-Nuremberg, Department of CS 12, Hardware-Software-Co-Design, Am Weichselgarten 3, D-91058 Erlangen, Germany, Tech. Rep. 01-2006, Mar. 2006.Google Scholar
  10. 10.
    P. Kocher, J. Jaffe, and B. Jun, “Differential Power Analysis,” Lect. Notes Comput. Sci., vol. 1666, pp. 388–397, 1999. Available at http://citeseer.ist.psu.edu/kocher99differential.html.
  11. 11.
    D. Agrawal, B. Archambeault, J. R. Rao, and P. Rohatgi, “The em Side-channel(s),” in CHES ‘02: Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems, Springer, London, UK, 2003, pp. 29–45.Google Scholar
  12. 12.
    A. Chandrakasan, S. Sheng, and R. Brodersen, “Low-Power CMOS Digital Design,” 1992. Available at http://citeseer.ist.psu.edu/chandrakasan95low.html.
  13. 13.
    L. Shang, A. S. Kaviani, and K. Bathala, “Dynamic power consumption in Virtex-II FPGA family,” in FPGA ‘02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, ACM Press, New York, NY, USA, 2002, pp. 157–164.Google Scholar
  14. 14.
    Xilinx, Inc., Virtex-II Platform FPGAS: Complete Data Sheet. ds031.pdf. Available at http://direct.xilinx.com/bvdocs/publications.
  15. 15.
    Digilent, Inc., Spartan-3 Board. S3BOARD.cfm. Available at http://www.digilentinc.com/info.
  16. 16.
    Opencores.org., Basic DES Crypto Core: Overview. Available at http://www.opencores.org/projects.cgi/web/basicdes.
  17. 17.
    D. S. Taubman and M. W. Marcellin, “JPEG 2000: Image Compression Fundamentals, Standards and Practice,” Kluwer, Norwell, MA, USA, 2001.Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  1. 1.Fraunhofer Institute for Integrated Circuits IISErlangenGermany
  2. 2.Department of Computer Science 12University of Erlangen-NurembergErlangenGermany

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