Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead


This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Line-pixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.

This is a preview of subscription content, log in to check access.


  1. 1.

    Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC), May. 2003.

  2. 2.

    S. Dutta, W. Wolf and A. Wolfe, “A Methodology to Evaluate Memory Architecture Design Tradeoffs for Video Signal Processors,” IEEE Trans. Circuits Syst. Video Technol, vol. 8, no. 1, 1998, pp. 36–53, Feb.

  3. 3.

    S.T. Fu, D.F. Zucker and M.J. Flynn, “Memory Hierarchy Synthesis of a Multimedia Embedded Processor,” IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD ’96, pp. 176–184, Oct. 1996.

  4. 4.

    T.-M. Liu et al., “A 125 μW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications,” IEEE J. Solid-State Circuits, vol. 42, no. 1, 2007, pp. 161–169, Jan.

  5. 5.

    T.-M. Liu et al., “An 865-μW H.264/AVC Video Decoder for Mobile Applications,” IEEE Asian Solid-State Circuits Conference, 2005, pp. 301–304, Nov.

  6. 6.

    Y. Hu, A. Simpson, K. McAdoo and J. Cush, “A high definition H.264/AVC hardware video decoder core for multimedia SoC’s,” IEEE International Symposium on Consumer Electronics, 2004, pp. 385–289, Sept.

  7. 7.

    Y.-W. Huang et al., “A 1.3TOPS H.264/AVC Single-Chip Encoder for HDTV Applications,” ISSCC Digest of Technical Papers, 2005, pp. 128–129, Feb.

  8. 8.

    H.-Y. Kang et al., “MPEG4 AVC/H.264 Decoder with Scalable Bus Architecture and Dual Memory Controller,” IEEE International Symposium on Circuits and Systems, 2004, pp. II-145–II-148, May.

  9. 9.

    C.-C. Lin et al., “A 160kGate 4.5 kB SRAM H.264 Video Decoder for HDTV Applications,” ISSCC Digest of Technical Papers, 2006, pp. 406–407, Feb.

  10. 10.

    S.-H. Wang et al. “A platform-based MPEG-4 advanced video coding (AVC) decoder with block level pipelining,” IEEE International Conference on Joint Conference, 2003, pp. 15–18, Dec.

  11. 11.

    T.-M. Liu, W.-P. Lee, T.-A. Lin and C.-Y. Lee, “A Memory-Efficient-Deblocking Filter for H.264/AVC Video Coding,” IEEE International Symposium on Circuit and System (ISCAS’05), 2005, pp. 2140–2143, May.

  12. 12.

    Y.-W. Huang, T.-W. Chen, B.-Y. Hsieh, T.-C. Wang, T.-H. Chang and L.-G. Chen, “Architecture Design for De-blocking Filter in H.264/JVT/AVC,” Proc. IEEE Intl. Conf. on Multimedia and Expo., vol.1, 2003, pp. 693–696, July.

  13. 13.

    S. Wuytack, J.-P. Diguet, V.M. Francky Catthoor and H.J. De Man, “Formalized Methodology for Data Reuse Exploration for Low-Power Hierarchical Memory Mappings,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst, vol. 6, no 4, 1998 pp. 529–537, Dec.

  14. 14.

    T.-M. Liu and C.-Y. Lee, “Memory-Hierarchy-Based Power Reduction for H.264/AVC Video Decoder,” IEEE International Symposium on VLSI International Symposium on Design, Automation and Test (VLSI-DAT’06), 2006, pp. 247–250, Apr.

  15. 15.

    J. M. Rabaey and M. Pedram, “Low Power Design Methodologies,” Kluwer Academic Publishers, 1995.

  16. 16.

    N.D. Zervas, K. Masselo, O.G. Koufopavlou and C.E. Goutis, “Power Exploration of Multimedia Applications Realization on Embedded Cores,” IEEE Int. Symp. Circuits Syst., vol. 4, 1999, pp. 378–381, June.

  17. 17.

    L. Wang, K. Panusopone, R. Gandhi, Y. Yu and A. Luthra, “Interlace coding tools for H.26L video coding”, VCEG-O37, Pattaya, 2001, Dec.

  18. 18.

    Micron® Technology Inc. MT48LC2M32B2 64Mb SDRAM. [Online Available]:

  19. 19.

    Micron® Technology Inc. The Micron® System-Power Calculator: SDRAM. [Online Available]: http://www.micron. com/products/dram/syscalc.html

Download references

Author information

Correspondence to Chen-Yi Lee.

Additional information

This work was supported by the National Science Council of Taiwan, R.O.C. under Grant NSC94-2215-E-009-046, and by the NCTU-MTK Research Program.

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Liu, T., Lee, C. Design of an H.264/AVC Decoder with Memory Hierarchy and Line-Pixel-Lookahead. J Sign Process Syst Sign Image 50, 69–80 (2008).

Download citation


  • H.264/AVC
  • memory hierarchy
  • lookahead
  • prediction