Abstract.
The transition activity on a data bus is a time series that determines power consumption on this data bus. The average values of power consumption and power grid voltage drop are proportional to average value of transition activity, i.e., transition probability. The fluctuation of power grid voltage drop appears as noise on power grid and its strength is determined by the second order statistics of transition activity, i.e., variance, auto-correlation function or power spectrum. In this paper, for the first time, simple accurate models for estimating variance and power spectrum of transition activity are proposed. The proposed models are based on linearly modeling spatial-time correlation of bit-level transition activity and result in low computational complexity but very good estimation accuracy. In addition, the dual bit type (DBT) [1, 2] model for estimating average transition activity was further developed. The previous DBT model was made complete with the equation derived in this paper for computing transition probability beyond breakpoint BP 1. Besides DSP computational architecture and algorithm designs, the proposed simple models are of great significance for power grid noise decoupling and chip floor-planning.
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Lijun Gao (S’99–M’01) received B.E. and M.E. degrees in Communication & Electronic Systems from Tsinghua University, Beijing, China, in 1986 and 1988, respectively. He received his PhD degree in Elecrical & Computer Engineering from University of Minnesota, Minneapolis, USA, in 2001. He is also an MS degree candidate in Computer & Information Science at University of Minnesota, Minneapolis.
Dr. Gao is currently with Medtronic Inc., Minneapolis, MN, and working on DSP design for pacemaker. From 2001 to 2003, he was with Bermai Inc., Minnetonka, MN and working on the design of wireless LAN (802.11a/11b) chipsets. In 2001, he worked in the R & D division of GlobeSpan Semiconductor Inc., Red Bank, NJ. From 1988 to 1991, he was a faculty member with Tsinghua University, Beijing, China. From 1991 to 1996, he was a R & D engineer with the Institute of Software, Chinese Academy of Science, Beijing, China. For the period of 1991 to 1993, he was a visiting R & D engineer at Onflo Computer Co. Hong Kong.
Dr. Gao received the Science & Technology awards from the National Education Council, China, in 1994 for his contribution to radar signal processing while he was at Tsinghua University, and from the ministry of Electronic Industry, China, in 1995 for his contribution to the CJK Ideograph Unification in ISO 10646 (Unicode).
His current reserach interest includes the algorithm/architecture/ circuit for VLSI design, the computational aspects of digital signal processing (DSP) and programmable DSP processor. Specifically, his focus is on the deep-submicron VLSI design, power estimation/low power design, computer arithmetic, finite field arithmetic, error control coding, cryptography, adaptive filters, equalization, beamformer, special-purpose processors and FPGA/reconfigurable computing.
Keshab K. Parhi (S’85-M’88–SM’91-F’96) Keshab K. Parhi received his B.Tech., MSEE, and Ph.D. degrees from the Indian Institute of Technology, Kharagpur, the University of Pennsylvania, Philadelphia, and the University of California at Berkeley, in 1982, 1984, and 1988, respectively. He has been with the University of Minnesota, Minneapolis, since 1988, where he is currently Distinguished McKnight University Professor in the Department of Electrical and Computer Engineering. His research addresses VLSI architecture design and implementation of physical layer aspects of broadband communications systems. He is currently working on error control coders and cryptography architectures, high-speed transceivers, ultra wideband systems, quantum error control coders and quantum cryptography. He has published over 350 papers, has authored the text book VLSI Digital Signal Processing Systems (Wiley, 1999) and coedited the reference book Digital Signal Processing for Multimedia Systems (Marcel Dekker, 1999).
Dr. Parhi is the recipient of numerous awards including the 2004 F.E. Terman award by the American Society of Engineering Education, the 2003 IEEE Kiyo Tomiyasu Technical Field Award, the 2001 IEEE W.R.G. Baker prize paper award, and a Golden Jubilee award from the IEEE Circuits and Systems Society in 1999. He has served on the editorial boards of the IEEE TRANSACTIONS ON CAS, CAS-II, VLSI Systems, Signal Processing, Signal Processing Letters, and currently serves on editorial board of the IEEE Signal Processing Magazine, and is the curent Editor-in-Chief of the IEEE Trans. on Circuits and Systems–I (2004–2005 term). He has served as technical program cochair of the 1995 IEEE VLSI Signal Processing workshop and the 1996 ASAP conference, and as the general chair of the 2002 IEEE Workshop on Signal Processing Systems. He was a distinguished lecturer for the IEEE Circuits and Systems society during 1996–1998. He currently serves on the Board of Governors of the IEEE Circuits and Systems Society. He was elected a Fellow of IEEE in 1996.
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Gao, L., Parhi, K. Models for Architectural Power and Power Grid Noise Analysis on Data Bus. J VLSI Sign Process Syst Sign Image Video Technol 44, 25–46 (2006). https://doi.org/10.1007/s11265-006-4176-2
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DOI: https://doi.org/10.1007/s11265-006-4176-2