A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures

  • Ivano Barbieri
  • Massimo Bariani
  • Alberto Cabitto
  • Marco Raggio
Article

Abstract

The increasing of computational power requirements for DSP and Multimedia application and the needs of easy-to-program development environment has driven recent programmable devices toward Very Long Instruction Word (VLIW) [1] architectures and Hw-Sw co-design environments [2]. VLIW architecture allows generating optimized machine code from high-level languages exploiting Instruction Level Parallelism (ILP) [3]. Furthermore, applications requirements and time to market constraints are growing dramatically moving functionalities toward System on Chip (SoC) direction. This paper presents VLIW-SIM, an Application-Driven Architecture-design approach based on Instruction Set simulation. VLIW architectures and Instruction Set simulation were chosen to fulfill multimedia domain requirements and to implement an efficient Hw-Sw co-design environment. The VLIW-SIM simulation technology is based on pipeline status modeling, Simulation cache and Simulation Oriented Hw description. An effective support for Hw-Sw co-design requires high simulation performance (in terms of Simulated Instruction per Second—SIPS), flexibility (the ability to represent a number of different architectures) and cycle accuracy. There is a strong trade-off between these features: cycle accurate or close to cycle accurate simulation have usually low performance [4, 5]. Good simulation performance can be obtained loosing the simulator flexibility. Moreover SoC simulation requires a further degree of flexibility in simulating different components (core, co-processors, memories, buses). The proposed approach is focused on interpretative (not compiled [6]) re-configurable Instruction Set Simulator (ISS) in order to support both application design and architecture exploration. VLIW-SIM main features are: efficient host resource allocation, Instruction Set and Architecture description Flexibility (Instruction Set Dynamic Generation and Simulation Oriented Hardware Description), Step by step pipeline status tracking, Simulation Speed and Accuracy. Performance of simulation test for three validation case studies (TI TMS320C62x, TI TMS320C64x and ST200) are reported.

Keywords

architecture exploration VLIW DSP multimedia Hw-Sw co-design simulation ISA flexibility simulation speed simulation accuracy system on chip 

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References

  1. 1.
    Joseph A. Fisher, “Very Long Instruction Word Architectures and the ELI-512,” in Proceedings of the 10th Annual International Symposium on Computer Architecture, Stockholm, Sweden, June 1983.Google Scholar
  2. 2.
    F. Balarin, M. Chiodo, et al., Hardware-Software Co-Design of Embedded Systems—The POLIS Approach, Kluwer Academic Publishers, 1997.Google Scholar
  3. 3.
    B.R. Rau, and J.A. Fisher, “Instruction Level Parallelism,” The Journal of Supercomputing, vol. 7 May 1993.Google Scholar
  4. 4.
    K. Olukotun, M. Heinrich, and D. Ofelt, “Digital System Simulation: Methodologies and Examples,” in Proc. Design Automation Conf., June 1998, pp. 658–663.Google Scholar
  5. 5.
    J. Rowson, “Hardware/Software Co-Simulation,” in Proc. Design Automation Conference, June 1994, pp. 439–440.Google Scholar
  6. 6.
    C. Mills, S.C. Ahalt, and J. Fowler, “Compiled Instruction Set Simulation,” Software–Practice and Experience, vol. 21, Aug. 1991, pp. 877–889.CrossRefGoogle Scholar
  7. 7.
    P. Faraboschi, G. Desoli, and J.A. Fisher “The Latest Word in Digital and Media Processing,” IEEE Signal Processing Magazine, March 1998.Google Scholar
  8. 8.
    P. Lapsley, J. Bier, A. Shoham, and E.A. Lee, “DSP Processor Fundamentals: Architectures and Features,” IEEE Press Series on Signal Processing, 1996.Google Scholar
  9. 9.
    Berkeley Design Technology Inc, “VLIW Architectures for DSP,” DSP World/ICSPAT, Orlando Florida, November 1999.Google Scholar
  10. 10.
    A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr, “A Novel Methodology for the Design of Application-Specific Instruction-Set Processors (ASIPs) Using a Machine Description Language,” IEEE Transaction on Computer-Aied Design of Integrated Circuits and System, vol. 20, no. 11, 2001.Google Scholar
  11. 11.
    R.B. Lee and M.D. Smith, “Media Processing: A New Design Target, IEEE Micro, Aug. 1996.Google Scholar
  12. 12.
    TI, TMS320C62x/C67x CPU and Instruction Set, Reference Guide, 1998.Google Scholar
  13. 13.
    TI, TMS320C64x Technical Overview, September 2000.Google Scholar
  14. 14.
    P. Faraboschi, J. Fisher, G. Brown, G. Desoli, and F. Homewood, “Lx: A Technology Platform for Customizable VLIW Embedded Processing,” ISCA Vancouver, Canada, June 2000.Google Scholar
  15. 15.
    A. Jemai, P. Kission, and A. Jerraya, “Combining Behavioral synthesis and Architectural simulation,” ASPDAC 1997.Google Scholar
  16. 16.
    A. Jemai, P. Kission, and A.A. Jerraya, “Architectural Simulation in the Context of Behavioral Synthesis,” DATE98, Paris, France, Feb. 1998.Google Scholar
  17. 17.
    P. Lieverse, P. Van der Wolf, E. Deprettere, and K. Vissers, “A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems,” SIPS99, IEEE Workshop on Signal Processing Systems, Taipei, Taiwan, Oct. 1999.Google Scholar
  18. 18.
    Eric Schnarr, Mark D. Hill, and James R. Larus, “Facile: A Language and Compiler for High-Performance Processor Simulators,” in PLDI2001, ACM SIGPLAN Conference on Programming Language Design and Implementation, Snowbird, Utah, USA, June 2001.Google Scholar
  19. 19.
    E. Schnarr and J.R. Larus, “Fast Out-Of-Order Processor Simulation Using Memoization,” ASPLOS98, San Jose CA, Oct. 1998.Google Scholar
  20. 20.
    J. Zhu and D.D. Gajski “An Ultra-Fast Instruction Set Simulator,” IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 10, no. 3, June 2002.Google Scholar
  21. 21.
    J.W. Ahn, S.M. Moon, aand W. Sung, “Efficient Compiled Simulation System for VLIW Code Verification,” in IEEE Annual Simulation Symposium, Boston, MA, USA, April 1998.Google Scholar
  22. 22.
    J. Liu, M. Lajolo, and A. Sangiovanni-Vincentelli, “Software Timing Analysis Using SW/HW Cosimulation and Instruction Set Simulator,” in 6th International Workshop on Hardware/Software Codesign, Seattle, Washington, USA, March 1998.Google Scholar
  23. 23.
  24. 24.
    L. Guerra, J. Fitzner, D. Talukdar, C. Schlaeger, B. Tabbara, and V. Zivojnovic, “Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification,” in DAC99 36th Annual Design Automation Conference, New Orleans, LA, USA, June 1999.Google Scholar
  25. 25.
    A. Baghdadi, D. Lyonnard, N.E. Zergainoh, and A.A. Jerraya, “An Efficient Architecture Model for Systematic Design of Application-Specific Multiprocessor SoC,” DATE01 Design, Automation, and Test in Europe, Munich, Germany, March 2001.Google Scholar
  26. 26.
    Murthy Durbhakula, Vijay S. Pai, and Sarita V. Adve, “Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors,” in HPCA99 Fifth International Symposium on High Performance Computer Architecture, Orlando, Florida, USA, Jan. 1999.Google Scholar
  27. 27.
    Berkeley Design Technology Inc, “Choosing a DSP Processor,” White Paper 2000, http://www.bdti.com.
  28. 28.
    I. Barbieri, M. Bariani, and M. Raggio, “C6XSIM: A VLIW Architecture Simulation Innovative Approach,” DCIS ‘99, Palma de Maiorca, Spain, Nov. 1999.Google Scholar
  29. 29.
    I. Barbieri, M. Bariani, and M. Raggio, “A VLIW Architecture Simulator Innovative Approach for HW-SW Co-Design,” in ICME2000—International Conference on Multimedia and Expo 2000, New York City, July 2000.Google Scholar
  30. 30.
    I. Barbieri, M. Bariani, and M. Raggio, “Multimedia Application Driven Instruction Set Architecture Simulation,” in ICME2002 - International Conference on Multimedia and Expo 2002, Lausanne, Aug. 2002.Google Scholar
  31. 31.
    R.K. Gupta and G. De Micheli, “Hardware-Software Cosynthesis for Digital Systems,” IEEE Design and Test of Computers, Sep. 1993.Google Scholar
  32. 32.
    S. Carr, “Combining Optimization for Cache and Instruction-Level Parallelism,” in Proceedings of the IFIP WG 10.3 Working Conference on Parallel Architectures and Compilation Techniques, PACT ‘96, Oct. 1996, pp. 238–247.Google Scholar
  33. 33.
    Vijay S. Pai, and Sarita Adve, “Code Transformations to Improve Memory Parallelism,” The Journal of Instruction-Level Parallelism, May 2000.Google Scholar
  34. 34.
    J. Bruns and C. Müller-Schloer, “An Integrated System-Level Modelling and Simulation Environment,” ESM ‘99 13th European Simulation Multiconference, Warsaw Poland, June 1999.Google Scholar
  35. 35.
    AXYS Design Automation Inc, “MaxSim Developer Suite User’s Guide Version 3.0,” Document Version 1.04 September 9th, 2002.Google Scholar
  36. 36.
    AXYS® Design Automation, Inc, http://www.axysdesign.com/.
  37. 37.
    ITU-T Recommendation H.263, “Video Coding for Low Bitrate Communication,” Feb. 1998.Google Scholar
  38. 38.
    ITU-T Recommendation G.723.1, “Dual Rate Speech Coder for Multimedia Communication Transmitting at 5.3 and 6.3 kbit/s,” March 1998.Google Scholar
  39. 39.
    ITU-T Recommendation G.726, “40, 32,24, 16 Kbit/Sec Adaptive Differential Pulse Code Modulation (ADPCM),” Nov. 1990.Google Scholar

Copyright information

© Springer Science + Business Media, Inc. 2005

Authors and Affiliations

  • Ivano Barbieri
    • 1
  • Massimo Bariani
    • 1
  • Alberto Cabitto
    • 1
  • Marco Raggio
    • 1
  1. 1.Department of Biophysical and Electronic EngineeringUniversity of GenovaGenovaItaly

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