Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging
- 160 Downloads
Medical image processing in general and computerized tomography (CT) in particular can benefit greatly from hardware acceleration. This application domain is marked by computationally intensive algorithms requiring the rapid processing of large amounts of data. To date, reconfigurable hardware has not been applied to the important area of image reconstruction. For efficient implementation and maximum speedup, fixed-point implementations are required. The associated quantization errors must be carefully balanced against the requirements of the medical community. Specifically, care must be taken so that very little error is introduced compared to floating-point implementations and the visual quality of the images is not compromised. In this paper, we present an FPGA implementation of the parallel-beam backprojection algorithm used in CT for which all of these requirements are met. We explore a number of quantization issues arising in backprojection and concentrate on minimizing error while maximizing efficiency. Our implementation shows approximately 100 times speedup over software versions of the same algorithm running on a 1 GHz Pentium, and is more flexible than an ASIC implementation. Our FPGA implementation can easily be adapted to both medical sensors with different dynamic ranges as well as tomographic scanners employed in a wider range of application areas including nondestructive evaluation and baggage inspection in airport terminals.
Keywordsbackprojection medical imaging tomography FPGA fixed point arithmetic
Unable to display preview. Download preview PDF.
- 2.M.A. Wu, “ASIC Applications in Computed Tomography Systems,” in Proceedings of Fourth Annual IEEE International ASIC Conference and Exhibit, Rochester, NY, USA, 1991, pp. P1–3/1–4.Google Scholar
- 4.I. Agi, P.J. Hurst, and K.W. Current, “A VLSI Architecture for High-Speed Image Reconstruction: Considerations for a Fixed-Point Architecture,” in Proceedings of SPIE, Parallel Architectures for Image Processing, vol. 1246, 1990, pp. 11–24.Google Scholar
- 6.C.B. Luiz Maltar, Felipe M.G. Franca, V.C. Alves, and C.L. Amorim, “Reconfigurable Hardware for Tomographic Processing,” in Proceedings of the XI Brazilian Symposium on Integrated Circuit Design, Rio de Janeiro/RJ: IEEE Computer Society Press, 1998, pp. 19–24.Google Scholar
- 9.C.B. Luiz Maltar, F.M.G. Franca, V.C. Alves, and C.L. Amorim, “An FPGA-Based Fan Beam Image Reconstruction Module”, in Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa, CA, USA, April 1999, pp. 331–332.Google Scholar
- 10.R. Yu, R. Ning, and B. Chen, “High Speed Cone Beam Reconstruction on PC,” SPIE Medical Imaging 2001, San Diego, CA, Feb. 17–22, 2001, pp. 964–973.Google Scholar
- 11.I. Goddard and M. Trepanier, “High-Speed Cone-Beam Reconstruction: An Embedded Systems Approach”, SPIE Medical Imaging 2002, San Diego, CA, Feb 24–26, 2002, pp. 483–491.Google Scholar
- 12.J. Bins, B. Draper, W. Bohm, and W. Najjar, “Precision vs. Error in JPEG Compression,” Parrallel and Distributed Methods for Image Processing III (SPIE), Denver CO, Jul 22, 1999, pp. 76–87.Google Scholar
- 13.S. Coric, M. Leeser, E. Miller, and M. Trepanier, “Parallel-Beam Backprojection: an FPGA Implementation Optimized for Medical Imaging,” in Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA02), February, 2002, pp. 217–226.Google Scholar
- 15.http://email@example.comfirstname.lastname@example.org, last accessed Nov 14, 2002
- 16.Z. Guo, W. Najjar, F. Vahid, and K. Vissers, “A Quantitative Analysis of the Speedup Factors of FPGAs over processors,” in Twelfth ACM International Symposium on Field-Programmable Gate Arrays (FPGA04), February, 2004, pp. 162–170.Google Scholar