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Design and analysis of SIC: a provably timing-predictable pipelined processor core

  • Sebastian HahnEmail author
  • Jan Reineke
Article
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Part of the following topical collections:
  1. Special Issue on Addressing the Real-Time Challenges of Multicore Architectures

Abstract

We introduce the strictly in-order core (SIC), a timing-predictable pipelined processor core. SIC is provably timing compositional and free of timing anomalies. This enables precise and efficient worst-case execution time (WCET) and multi-core timing analysis. SIC’s key underlying property is the monotonicity of its transition relation w.r.t. a natural partial order on its microarchitectural states. This monotonicity is achieved by carefully eliminating some of the dependencies between consecutive instructions from a standard in-order pipeline design. We present a formal proof framework based on satisfiability modulo theories that is able to automatically verify SIC’s timing predictability. SIC preserves most of the benefits of pipelining: it is only about 6–7% slower than a conventional non-strict in-order pipelined processor. Its timing predictability enables orders-of-magnitude faster WCET and multi-core timing analysis than conventional designs.

Keywords

Timing analysis Timing predictability Timing anomalies Timing compositionality Hardware design 

Notes

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Saarland UniversitySaarbrückenGermany

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