Real-Time Systems

, Volume 54, Issue 2, pp 389–423 | Cite as

Patmos: a time-predictable microprocessor

  • Martin Schoeberl
  • Wolfgang Puffitsch
  • Stefan Hepp
  • Benedikt Huber
  • Daniel Prokesch


Current processors provide high average-case performance, as they are optimized for general purpose computing. However, those optimizations often lead to a high worst-case execution time (WCET). WCET analysis tools model the architectural features that increase average-case performance. To keep analysis complexity manageable, those models need to abstract from implementation details. This abstraction further increases the WCET bound. This paper presents a way out of this dilemma: a processor designed for real-time systems. We design and optimize a processor, called Patmos, for low WCET bounds rather than for high average-case performance. Patmos is a dual-issue, statically scheduled RISC processor. A method cache serves as the cache for the instructions and a split cache organization simplifies the WCET analysis of the data cache. To fill the dual-issue pipeline with enough useful instructions, Patmos relies on a customized compiler. The compiler also plays a central role in optimizing the application for the WCET instead of average-case performance.


Real-time systems Time-predictable architecture Worst-case execution time 



We would like to thank Tommy Thorn for the ongoing discussions on computer architecture, processor design, and optimization for an FPGA implementation. We would like to thank Florian Brandner for discussions on the Patmos instruction set, the initial implementation of the software simulator of Patmos, and the initial port of LLVM for Patmos. We would like to thank Sahar Abbaspour for helping on a first VHDL version of the pipeline. This work was partially funded under the European Union’s 7th Framework Programme under Grant Agreement No. 288008: Time-predictable Multi-Core Architecture for Embedded Systems (T-CREST). This work is part of the project “Hard Real-Time Embedded Multiprocessor Platform - RTEMP” and received partial funding from the Danish Research Council for Technology and Production Sciences under Contract No. 12-127600.


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Authors and Affiliations

  1. 1.Department of Applied Mathematics and Computer ScienceTechnical University of DenmarkLyngbyDenmark
  2. 2.Institute of Computer LanguagesVienna University of TechnologyWienAustria
  3. 3.Institute of Computer EngineeringVienna University of TechnologyWienAustria

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