Real-Time Systems

, Volume 51, Issue 3, pp 274–313 | Cite as

Architecture aware semi partitioned real-time scheduling on multicore platforms

  • Mayank Shekhar
  • Harini Ramaprasad
  • Abhik Sarkar
  • Frank Mueller
Article
First Online:

Abstract

As real-time embedded systems integrate more and more functionality, they are demanding increasing amounts of computational power that can only be met by deploying them on powerful and scalable multicore architectures. The use of multicore architectures with on-chip memory hierarchies and shared communication infrastructure in the context of real-time systems poses several challenges for task scheduling. Semi-partitioned scheduling algorithms form a middle ground between the two extreme approaches, namely global and partitioned scheduling. In such an algorithm, a subset of tasks are partitioned onto cores and the remaining tasks are allowed to migrate in a pre-specified manner. By making most tasks non-migrating (partitioned), runtime migration overhead is minimized. On the other hand, by allowing some tasks to migrate among cores, schedulability is improved. In this paper, we present a predictable semi-partitioned scheduling algorithm for independent hard-real-time sporadic tasks executing on homogeneous multicore platforms using cache locking and locked cache migration. As part of the semi-partitioned scheduling algorithm, we propose two different task ordering schemes and two different schemes for the initial partitioning phase. Simulation results demonstrate the effectiveness of the proposed schemes in comparison to existing state-of-the-art techniques.

Keywords

Real-time scheduling Semi-partitioned Multi-core 
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Notes

Acknowledgments

This work was supported in part by NSF grants CNS-0905212, CNS-0905181, and CNS-1239246. Author’s addresses: Mayank Shekhar, Department of Electrical and Computer Engineering, Southern Illinois University Carbondale; Harini Ramaprasad, Department of Computer Science, University of North Carolina at Charlotte; Abhik Sarkar (current address), Intel Corporation, California; Frank Mueller, Department of Computer Science, North Carolina State University. A preliminary version of this work appeared in the Euromicro Conference on Real-Time Systems (ECRTS), 2012 Shekhar et al. (2012). This journal version motivates and proposes a novel task ordering scheme based on task migration characteristics (Sect. 4.3.1) and a novel Slack and Architecture Aware task allocation scheme (Sects. 4.3.4, 4.3.5). It presents simulation results for the newly proposed schemes and performs a detailed comparison between the new schemes and two existing schemes (Sect. 6).

References

  1. Anderson J, Srinivasan A (2000) Early-release fair scheduling. In: Euromicro conference on real-time systems, pp 35–43Google Scholar
  2. Anderson J, Bastoni A, Brandenburg B (2011) Is semi-partitioning practical ? In: Euromicro conference on real-time systems, pp 122–135Google Scholar
  3. Andersson B, Bletsas K (2008) Sporadic multiprocessor scheduling with few preemptions. In: Proceedings of the 2008 euromicro conference on real-time systems, ECRTS ’08, pp 243–252Google Scholar
  4. Baruah S (2007) Techniques for multiprocessor global schedulability analysis. In: IEEE real-time systems symposium, pp 119–128Google Scholar
  5. Baruah S, Cohen N, Plaxton C, Varvel D (1996) Proportionate progress: a notion of fairness in resource allocation. Algorithmica 15:600–625MATHMathSciNetCrossRefGoogle Scholar
  6. Bini E, Buttazzo GC (2005) Measuring the performance of schedulability tests. RTS 30(2):129–154MATHGoogle Scholar
  7. Burchard A, Liebeherr J, Oh Y, Son S (1995) New strategies for assigning real-time tasks to multiprocessor systems. IEEE Trans Comput 44(12):1429–1442MATHMathSciNetCrossRefGoogle Scholar
  8. Burns A, Davis RI, Wang P, Zhang F (2012) Partitioned EDF scheduling for multiprocessors using a \(C=D\) task splitting scheme. RTS 48:3–33MATHGoogle Scholar
  9. Chou CL, Marculescu R (2008) Contention aware application mapping for network-on-chip communication architecutres. In: International conference on computer design-ICCD, pp 164–169Google Scholar
  10. Crespo IRA, Mok A (1996) Improvement in feasibilty testing for real-time tasks. J Real-Time Syst 11(1):19–39CrossRefGoogle Scholar
  11. Davis RI, Burns A (2011) Improved priority assignment for global fixed priority pre-emptive scheduling in multi-processor real-time systems. RTS 47(1):1–40MATHGoogle Scholar
  12. Dhall S, Liu C (1978) On a real-time scheduling problem. Oper Res 26(1):127–140MATHMathSciNetCrossRefGoogle Scholar
  13. Dorin F, Yomsi PM, Goossens J, Richard P (2010) Semi-partitioned hard real-time scheduling with restricted migrations upon identical multiprocessor platforms. CoRR arXiv:1006.2637
  14. Goossens K, Dielissen J, Radulescu A (2005) Aethereal network on chip: concepts, architectures, and implementations. IEEE Des Test 22:414–421CrossRefGoogle Scholar
  15. Intel (2012) Intel’s single-chip cloud computer. http://Techresearch.intel.com/ProjectDetails.aspx?Id=1
  16. Kato S, Yamasaki N (2008) Portioned edf-based scheduling on multiprocessors. In: Proceedings of the 8th ACM international conference on Embedded software, pp 139–148Google Scholar
  17. Kato S, Yamasaki N, Ishikawa Y (2009) Semi-partitioned scheduling of sporadic task systems on multiprocessors. In: Euromicro conference on real-time systemsGoogle Scholar
  18. Lisper B, Vera X (2003) Data cache locking for higher program predictability. In: ACM SIGMETRICS international conference on measurement and modeling of computer systems, pp 272–282Google Scholar
  19. Livani MA, Kaiser J, Jia W (1999) Scheduling hard and soft real-time communication in a controller area network. In: IFAC/IFIP workshop on real-time programmingGoogle Scholar
  20. Moir M, Ramamurthy S (1999) Pfair scheduling of fixed and migrating periodic tasks on multiple resources. In: IEEE real-time systems symposium, pp 294–303Google Scholar
  21. Murali S, Micheli GD (2004) Bandwidth-constrained mapping of cores onto noc architectures. In: Design, automation and test in europe conference and exhibition, pp 896–901Google Scholar
  22. Puaut I (2006) Wcet-centric software-controlled instruction caches for hard real-time systems. In: ECRTS ’06: proceedings of the 18th euromicro conference on real-time systems, IEEE Computer Society, Washington, DC, USA, pp 217–226. doi: 10.1109/ECRTS.2006.32
  23. Puaut I, Decotigny D (2002) Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In: IEEE real-time systems symposium, pp 114–123Google Scholar
  24. Puaut I, Pais C (2007) Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison. In: Design, automation and test in Europe, EDA Consortium, San Jose, CA, USA, pp 1484–1489. http://portal.acm.org/citation.cfm?id=1266366.1266692
  25. Ramaprasad H, Mueller F (2010) Tightening the bounds on feasible preemptions. ACM Trans Embed Comput Syst 10:27:1–27:34Google Scholar
  26. Rhee CE, Jeong HY, Ha S (2004) Many-to-many core-switch mapping in 2-d mesh noc architectures. In: Computer design: IEEE international conference on VLSI in computers and processors, ICCD, pp 438–443Google Scholar
  27. Sarkar A, Mueller F, Ramaprasad H, Mohan S (2009) Push-assisted migration of real-time tasks in multi-core processors. In: ACM SIGPLAN conference on language, compiler, and tool support for embedded systems, pp 80–89Google Scholar
  28. Sarkar A, Mueller F, Ramaprasad H (2011) Predictable task migration for locked caches in multi-core systems. In: ACM SIGPLAN conference on language, compiler, and tool support for embedded systems, pp 131–140Google Scholar
  29. Shekhar M, Sarkar A, Ramaprasad H, Mueller F (2012) Semi-partitioned hard-real-time scheduling under locked cache migration in multicore systems. In: Euromicro conference on real-time systems, pp 331–340Google Scholar
  30. Shi Z, Burns A (2008) Edzl scheduling analysis. In: Second ACM/IEEE international symposium on networks-on-chip, pp 161–170Google Scholar
  31. Shi Z, Burns A (2010) Schedulability analysis and task mapping for real-time on-chip communication. Real Time Syst 46:360–385MATHCrossRefGoogle Scholar
  32. Srinivasan A, Anderson J (2002) Optimal rate-based scheduling on multiprocessors. In: ACM symposium on theory of computing, pp 189–198Google Scholar
  33. Suhendra V, Mitra T (2008) Exploring locking & partitioning for predictable shared caches on multi-cores. In: Design automation conference, ACM, New York, NY, USA, pp 300–303. doi:  10.1145/1391469.1391545. http://portal.acm.org/citation.cfm?id=1391469.1391545
  34. Tilera (2012) Tilera processor family. http://www.tilera.com/
  35. van den Brand J, Ciordas C, Goossens K, Basten T (2007) Congestion-controlled best-effort communication for networks-on-chip. In: Proceedings of the conference on Design, automation and test in EuropeGoogle Scholar
  36. Zhang F, Burns A (2008) Schedulability analysis for real-time systems with edf scheduling. IEEE Trans Comput 58(9):1250–1258MathSciNetCrossRefGoogle Scholar
  37. Zivojnovic V, Velarde J, Schlager C, Meyr H (1994) Dspstone: a DSP-oriented benchmarking methodology. In: Signal processing applications and technologyGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Mayank Shekhar
    • 1
  • Harini Ramaprasad
    • 2
  • Abhik Sarkar
    • 3
  • Frank Mueller
    • 3
  1. 1.Southern Illinois University CarbondaleCarbondaleUSA
  2. 2.University of North Carolina at CharlotteCharlotteUSA
  3. 3.North Carolina State UniversityRaleighUSA

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