Real-Time Systems

, Volume 50, Issue 5–6, pp 620–679 | Cite as

Parameter synthesis for hierarchical concurrent real-time systems

  • Étienne André
  • Yang Liu
  • Jun Sun
  • Jin-Song Dong
Article

Abstract

Modeling and verifying complex real-time systems, involving timing delays, are notoriously difficult problems. Checking the correctness of a system for one particular value for each delay does not give any information for other values. It is thus interesting to reason parametrically, by considering that the delays are parameters (unknown constants) and synthesizing a constraint guaranteeing a correct behavior. We present here Parametric Stateful Timed Communicating Sequential Processes, a language capable of specifying and verifying parametric hierarchical real-time systems with complex data structures. Although we prove that the synthesis is undecidable in general, we present several semi-algorithms for efficient parameter synthesis, which behave well in practice. This work has been implemented in a real-time model checker, PSyHCoS, and validated on a set of case studies.

Keywords

Real-time specification Parametric timed verification  Model checking Robustness 

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Étienne André
    • 1
  • Yang Liu
    • 2
  • Jun Sun
    • 3
  • Jin-Song Dong
    • 4
  1. 1.Université Paris 13, Sorbonne Paris Cité, LIPN, CNRS UMR 7030VilletaneuseFrance
  2. 2.School of Computer EngineeringNanyang Technological UniversitySingaporeSingapore
  3. 3.Singapore University of Technology and DesignSingaporeSingapore
  4. 4.School of ComputingNational University of SingaporeSingaporeSingapore

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