Timing predictability of cache replacement policies
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Hard real-time systems must obey strict timing constraints. Therefore, one needs to derive guarantees on the worst-case execution times of a system’s tasks. In this context, predictable behavior of system components is crucial for the derivation of tight and thus useful bounds. This paper presents results about the predictability of common cache replacement policies. To this end, we introduce three metrics, evict, fill, and mls that capture aspects of cache-state predictability. A thorough analysis of the LRU, FIFO, MRU, and PLRU policies yields the respective values under these metrics. To the best of our knowledge, this work presents the first quantitative, analytical results for the predictability of replacement policies. Our results support empirical evidence in static cache analysis.
KeywordsPredictability Timing analysis Cache analysis Cache replacement policies Hard real-time systems
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- Freescale Semiconductor Inc (2002) MPC750 RISC Microprocessor User Manual, Section 3.5.1. http://www.freescale.com/files/32bit/doc/ref_manual/MPC750UM.pdf
- Langenbach M, Thesing S, Heckmann R (2002) Pipeline modeling for timing analysis. In: Proceedings of the static analyses symposium (SAS), vol 2477, Madrid, Spain Google Scholar
- Malamy A, Patel R, Hayes N (October 1994) Methods and apparatus for implementing a pseudo-LRU cache memory replacement scheme with a locking feature. United States Patent 5029072 Google Scholar
- Thesing S (2004) Safe and precise WCET determinations by abstract interpretation of pipeline models. PhD thesis, Saarland University Google Scholar