Advertisement

A link-elimination partitioning approach for application graph mapping in reconfigurable computing systems

  • Seyed Mehdi Mohtavipour
  • Hadi Shahriar ShahhoseiniEmail author
Article
  • 3 Downloads

Abstract

Dynamic reconfiguration provides flexibility in the design and management of reconfigurable computing (RC) systems such that numerous applications would be mapped into limited resources simultaneously. As the mapping is a computationally intensive procedure in application compilation, a low-complex method is needed strongly for RC applications. In this paper, we propose a link-elimination partitioning approach for application graphs to reduce computations and reach an optimal solution faster as well. The link-elimination preprocessing step is performed by investigating the standard deviation of weights and removing lightweight links from the partitioning procedure. Based on the Laplacian matrix, a formulation method for detecting high-degree nodes as partition seeds has been generated. Moreover, a distance model for the region of implementation in resource graph has been introduced in this paper. In order to select among any rectangular shape of the resource graph, an average distance factor has been defined analytically. It has been proved that partitions with more connectivity must be implemented in a square-formed shape. Extensive experiments with random and benchmark graphs have been carried out to compare the proposed partitioning approach with the previous methods, and the results manifested that for fixed searching iterations, quality of solutions and time overhead have been improved 22% and 59%, respectively.

Keywords

Reconfigurable hardware Dynamic reconfiguration Application mapping Graph mapping 

Notes

References

  1. 1.
    Charitopoulos G, Koidis I, Papadimitriou K, Pnevmatikatos D (2017) Run-time management of systems with partially reconfigurable FPGAs. Integration 57:34–44CrossRefGoogle Scholar
  2. 2.
    Bassiri MM, Shahhoseini HS (2011) Configuration reusing in on-line task scheduling for reconfigurable computing systems. J Comput Sci Technol 26(3):463–474CrossRefGoogle Scholar
  3. 3.
    Bhasin S, Danger JL, Guilley S, He W (2015) Exploiting FPGA block memories for protected cryptographic implementations. ACM Trans Reconfig Technol Syst (TRETS) 8(3):16–28Google Scholar
  4. 4.
    Ronak B, Fahmy SA (2016) Mapping for maximum performance on FPGA DSP blocks. IEEE Trans Comput Aided Des Integr Circuits Syst 35(4):573–585CrossRefGoogle Scholar
  5. 5.
    Nangia R, Shukla NK (2018) Resource utilization optimization with design alternatives in FPGA based arithmetic logic unit architectures. Proc Comput Sci 132:843–848CrossRefGoogle Scholar
  6. 6.
    Rossi E, Damschen M, Bauer L, Buttazzo G, Henkel J (2018) Preemption of the partial reconfiguration process to enable real-time computing with FPGAs. ACM Trans Reconfig Technol Syst (TRETS) 11(2):10–24Google Scholar
  7. 7.
    Lebedev I, Cheng S, Doupnik A, Martin J, Fletcher C, Burke D, Lin M, Wawrzynek J (2010) MARC: a many-core approach to reconfigurable computing. In: International Conference on Reconfigurable Computing and FPGAs, pp 7–12Google Scholar
  8. 8.
    Bassiri MM, Shahhoseini HS (2009) On-line HW/SW partitioning and co-scheduling in reconfigurable computing systems. In: IEEE International Conference on Computer Science and Information Technology, pp 557–562Google Scholar
  9. 9.
    Elbirt AJ, Paar C (2000) An FPGA implementation and performance evaluation of the serpent block cipher. In: Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays, pp 33–40Google Scholar
  10. 10.
    Gautam A, Jain P (2015) FPGA implementation of dynamic key generation to enhance DES algorithm securities. Int J Eng Res Technol 4:673–677Google Scholar
  11. 11.
    Rao MG, Kumar PR, Prasad AM (2016) Implementation of real time image processing system with FPGA and DSP. In: IEEE International Conference Microelectronics, Computing and Communications (MicroCom), pp 1–4Google Scholar
  12. 12.
    Pandey JG, Karmakar A, Shekhar C, Gurunarayanan S (2015) An FPGA-based architecture for local similarity measure for image/video processing applications. In: 28th International Conference on IEEE VLSI Design (VLSID), pp 339–344Google Scholar
  13. 13.
    Jang JH, Lee SM, Gwon OS, Lee SE (2016) An FPGA based compression accelerator for Forex Trading System. In: Latifi S (ed) Information technology: new generations. Springer, Cham, pp 711–720CrossRefGoogle Scholar
  14. 14.
    Nane R, Sima VM, Pilato C, Choi J, Fort B, Canis A, Chen YT, Hsiao H, Brown S, Ferrandi F, Anderson J (2016) A survey and evaluation of FPGA high-level synthesis tools. IEEE Trans Comput Aided Des Integr Circuits Syst 35(10):1591–1604CrossRefGoogle Scholar
  15. 15.
    Vipin K, Fahmy SA (2018) FPGA dynamic and partial reconfiguration: a survey of architectures, methods, and applications. ACM Comput Surv (CSUR) 51(4):72CrossRefGoogle Scholar
  16. 16.
    Clemente JA, Beretta I, Rana V, Atienza D, Sciuto D (2014) A mapping-scheduling algorithm for hardware acceleration on reconfigurable platforms. ACM Trans Reconfig Technol Syst (TRETS) 7(2):9Google Scholar
  17. 17.
    Hauck S, DeHon A (2010) Reconfigurable computing: the theory and practice of FPGA-based computation, vol 1. Elsevier, AmsterdamzbMATHGoogle Scholar
  18. 18.
    Daryanavard H, Eshghi M, Jahanian A (2015) A fast placement algorithm for embedded just-in-time reconfigurable extensible processing platform. J Supercomput 71(1):121–143CrossRefGoogle Scholar
  19. 19.
    Zhu K, Wong DF (1992) On channel segmentation design for row-based FPGAs. In: IEEE/ACM International Conference on Computer-Aided Design, pp 26–29Google Scholar
  20. 20.
    Yuan FL, Wang CC, Yu TH, Marković D (2015) A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing. IEEE J Solid-State Circuits 50(1):137–149CrossRefGoogle Scholar
  21. 21.
    Wang X, Liu H, Yu Z (2016) A novel heuristic algorithm for IP block mapping onto mesh-based networks-on-chip. J Supercomput 72(5):2035–2058CrossRefGoogle Scholar
  22. 22.
    Tosun S, Ozturk O, Ozkan E, Ozen M (2015) Application mapping algorithms for mesh-based network-on-chip architectures. J Supercomput 71(3):995–1017CrossRefGoogle Scholar
  23. 23.
    Drezner Z (2015) The quadratic assignment problem. In: Laporte G, Nickel S, da Gama FS (eds) Location science. Springer, Cham, pp 345–363Google Scholar
  24. 24.
    Ababei C (2009) Speeding up FPGA placement via partitioning and multithreading. Int J Reconfig Comput 2009:6–17Google Scholar
  25. 25.
    Singh AK, Shafique M, Kumar A, Henkel J (2013) Mapping on multi/many-core systems: survey of current and emerging trends. In: 50th IEEE Design Automation Conference (DAC), pp 1–10Google Scholar
  26. 26.
    Benyamina AH, Boulet P, Benhaoua K (2015) Static and dynamic mapping heuristics for multiprocessor systems-on-chip. In: Gamatié A (ed) Computing in research and development in Africa. Springer, Cham, pp 229–247Google Scholar
  27. 27.
    Maqsood T, Ali S, Malik SU, Madani SA (2015) Dynamic task mapping for network-on-chip based systems. J Syst Architect 61(7):293–306CrossRefGoogle Scholar
  28. 28.
    Maqsood T, Bilal K, Madani SA (2016) Congestion-aware core mapping for network-on-chip based systems using betweenness centrality. Future Gener Comput Syst 82:459–471CrossRefGoogle Scholar
  29. 29.
    Lotfifar F, Shahhoseini HS (2009) A low-complexity task scheduling algorithm for heterogeneous computing systems. In: Third Asia International Conference on Modelling and Simulation, pp 596–601Google Scholar
  30. 30.
    Tosun S, Ozturk O, Ozen M (2009) An ILP formulation for application mapping onto network-on-chips. In: IEEE International Conference on Application of Information and Communication Technologies, pp 1–5Google Scholar
  31. 31.
    Hu J, Marculescu R (2005) Energy-and performance-aware mapping for regular NoC architectures. IEEE Trans Comput Aided Des Integr Circuits Syst 24(4):551–562CrossRefGoogle Scholar
  32. 32.
    Mishra A, Vakharia D, Hati AJ, Raju KS (2014) Hardware software partitioning of task graph using genetic algorithm. In: IEEE Recent Advances and Innovations in Engineering (ICRAIE), pp 1–5Google Scholar
  33. 33.
    Al-Wattar A, Areibi S, Grewal G (2016) Efficient mapping and allocation of execution units to task graphs using an evolutionary framework. ACM SIGARCH Comput Archit News 43(4):46–51CrossRefGoogle Scholar
  34. 34.
    Mollajafari M, Shahhoseini HS (2016) An efficient ACO-based algorithm for scheduling tasks onto dynamically reconfigurable hardware using TSP-likened construction graph. Appl Intell 45(3):695–712CrossRefGoogle Scholar
  35. 35.
    Larumbe F, Sanso B (2013) A tabu search algorithm for the location of data centers and software components in green cloud computing networks. IEEE Trans Cloud Comput 1(1):22–35CrossRefGoogle Scholar
  36. 36.
    Zhu D, Chen L, Pinkston TM, Pedram M (2015) TAPP: temperature-aware application mapping for NoC-based many-core processors. In: Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, pp 1241–1244Google Scholar
  37. 37.
    Tosun S, Ozturk O, Ozkan E, Ozen M (2015) Application mapping algorithms for mesh-based network-on-chip architectures. J Supercomput 71(3):995–1017CrossRefGoogle Scholar
  38. 38.
    Hager WW, Krylyuk Y (1999) Graph partitioning and continuous quadratic programming. SIAM J Discrete Math 12(4):500–523MathSciNetCrossRefGoogle Scholar
  39. 39.
    Sellmann M, Sensen N, Timajev L (2003) Multicommodity flow approximation used for exact graph partitioning. In: European Symposium on Algorithms, pp 752–764CrossRefGoogle Scholar
  40. 40.
    Karypis G, Kumar V (1998) A fast and high quality multilevel scheme for partitioning irregular graphs. SIAM J Sci Comput 20(1):359–392MathSciNetCrossRefGoogle Scholar
  41. 41.
    Karypis G, Kumar V (1998) Multilevel scheme k-partitioning scheme for irregular graphs. J Parallel Distrib Comput 48(1):96–129CrossRefGoogle Scholar
  42. 42.
    Anderson R, Lang K (2008) An algorithm for improving graph partitions. In: 19th ACM–SIAM Symposium On Discrete Mathematics, pp 651–660Google Scholar
  43. 43.
    Schanberger S (2004) Partitioning FEM graphs using diffusion. In: IEEE Symposium on Parallel and Distributed ProcessingGoogle Scholar
  44. 44.
    Riolo MA, Newman MEJ (2014) First-principles multiway spectral partitioning of graphs. Journal of Complex Networks 2(2):121–140CrossRefGoogle Scholar
  45. 45.
    Benson AR, Gleich DF, Leskovec J (2015) Tensor spectral clustering for partitioning higher-order network structures. In: Proceedings of the 2015 SIAM International Conference on Data Mining, pp 118–126Google Scholar
  46. 46.
    Chen PY, Hero AO (2014) Local Fiedler vector centrality for detection of deep and overlapping communities in networks. In: IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp 1120–1124Google Scholar
  47. 47.
    Li L, Sun J, Li W, Lv Z, Guan F (2015) Hardware/software partitioning based on hybrid genetic and tabu search in the dynamically reconfigurable system. Int J Control Autom 8(1):29–36CrossRefGoogle Scholar
  48. 48.
    Ding L, Guo T, Lu Z (2015) A hybrid method for dynamic mesh generation based on radial basis functions and Delaunay graph mapping. Adv Appl Math Mech 7(3):338–356MathSciNetCrossRefGoogle Scholar
  49. 49.
    Li T, Bhattacharyya S, Sarkar P, Bickel PJ, Levina E (2018) Hierarchical community detection by recursive bi-partitioning. arXiv preprint arXiv:1810.01509
  50. 50.
    Ruan J, Zhang W (2007) An efficient spectral algorithm for network community discovery and its applications to biological and social networks. In: IEEE International Conference on Data Mining, pp 643–648Google Scholar
  51. 51.
    Mezić I, Fonoberov VA, Fonoberova M, Sahai T (2018) Spectral complexity of directed graphs and application to structural decomposition. arXiv preprint arXiv:1808.06004
  52. 52.
    Marwedel P (2011) Application mapping. In: Embedded System Design. Embedded Systems. Springer, DordrechtCrossRefGoogle Scholar
  53. 53.
    Hredzak B, Diessel O (2011) Optimization of placement of dynamic network-on-chip cores using simulated annealing. In: 37th Annual Conference on IEEE Industrial Electronics Society, pp 2400–2405Google Scholar
  54. 54.
    Banerjee P, Shenoy N, Choudhary A, Hauck S, Bachmann C, Haldar M, Joisha P, Jones A, Kanhare A, Nayak A, Periyacheri S (2000) A MATLAB compiler for distributed, heterogeneous, reconfigurable computing systems. In: IEEE Symposium on Field-Programmable Custom Computing Machines, pp 39–48Google Scholar
  55. 55.
    Juve G, Chervenak A, Deelman E, Bharathi S, Mehta G, Vahi K (2013) Characterizing and profiling scientific workflows. Future Gener Comput Syst 29:682–692CrossRefGoogle Scholar
  56. 56.
    Newman ME, Girvan M (2004) Finding and evaluating community structure in networks. Phys Rev E 69(2):026113CrossRefGoogle Scholar
  57. 57.
    Mhadhbi I, Othman SB, Saoud SB (2016) A comprehensive survey on hardware/software partitioning process in co-design. Int J Comput Sci Inf Secur 14(3):263–275Google Scholar
  58. 58.
    Chan TF, Cong J, Romesis M, Shinnerl JR, Sze K, Xie M (2005) mPL6: a robust multilevel mixed-size placement engine. In: ACM Proceedings of the 2005 International Symposium on Physical Design, pp 227–229Google Scholar
  59. 59.
    Montone A, Santambrogio MD, Sciuto D, Memik SO (2010) Placement and floorplanning in dynamically reconfigurable FPGAs. ACM Trans Reconfig Technol Syst (TRETS) 3(4):24–57Google Scholar
  60. 60.
    Hassan AS, Morgan AA, El-Kharashi MW (2017) Clustered networks-on-chip: simulation and performance evaluation. Int J Comput Digit Syst 6(02):51–61CrossRefGoogle Scholar
  61. 61.
    Steiger C, Walder H, Platzner M, Thiele L (2003) Online scheduling and placement of real-time tasks to partially reconfigurable devices. In: 24th IEEE Real-Time Systems Symposium, pp 224–225Google Scholar
  62. 62.
    Marconi T (2014) Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays. Comput Electr Eng 40(4):1215–1237CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  • Seyed Mehdi Mohtavipour
    • 1
  • Hadi Shahriar Shahhoseini
    • 1
    Email author
  1. 1.School of Electrical EngineeringIran University of Science and TechnologyTehranIran

Personalised recommendations