A parallel pattern for iterative stencil + reduce

  • M. Aldinucci
  • M. Danelutto
  • M. Drocco
  • P. Kilpatrick
  • C. Misale
  • G. Peretti Pezzi
  • M. Torquati
Article

Abstract

We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.

Keywords

Parallel patterns OpenCL GPUs Heterogeneous multi-cores 

Notes

Acknowledgments

This work was supported by EU FP7 project REPARA (No. 609666), the EU H2020 Project RePhrase (No. 644235), and by the NVidia GPU Research Center at the University of Torino.

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Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • M. Aldinucci
    • 2
  • M. Danelutto
    • 1
  • M. Drocco
    • 2
  • P. Kilpatrick
    • 3
  • C. Misale
    • 2
  • G. Peretti Pezzi
    • 4
  • M. Torquati
    • 1
  1. 1.Department of Computer ScienceUniversity of PisaPisaItaly
  2. 2.Department of Computer ScienceUniversity of TurinTurinItaly
  3. 3.Department of Computer ScienceQueen’s University BelfastBelfastUK
  4. 4.Swiss National Supercomputing CentreLuganoSwitzerland

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