The Journal of Supercomputing

, Volume 72, Issue 3, pp 1092–1124 | Cite as

Design procedures and NML cost analysis of reversible barrel shifters optimizing garbage and ancilla lines

  • Himanshu ThapliyalEmail author
  • Carson Labrado
  • Ke Chen


Reversible computing generates a unique output from each input and vice versa. In addition, conservative reversible logic is useful to design ultra-low-power nanocomputing circuits, circuits for quantum computing, and nanocircuits that are testable in nature. Reversible computing circuits require ancilla inputs and garbage outputs to maintain reversibility. An ancilla input is the constant input in a reversible circuit. A garbage output is an output which exists in the circuit just to maintain one-to-one mapping but is not a primary nor a useful output. An efficient reversible circuit will have a minimal number of garbage and ancilla bits. Furthermore, the barrel shifter is one of the main computing systems having applications in high-speed digital signal processing, floating-point arithmetic, field programmable gate arrays, and central processing units. A barrel shifter can shift and rotate multiple bits in a single clock cycle. In this work, we proposed five designs of barrel shifters based on reversible computing that are optimized in terms of the number of garbage outputs and the number of ancilla inputs. To achieve this goal, a new super conservative reversible logic gate (SCRL gate) has been proposed. The SCRL gate has 1 control input depending on the value of which it can swap any two \(n-1\) data inputs. The five proposed designs consist of reversible right rotator, reversible logical right shifter, reversible arithmetic right shifter, reversible universal right shifter, and reversible universal bidirectional shifter. The proposed designs of reversible barrel shifters are compared with the existing works in the literature and have shown improvements ranging from 8.57 to 91.62 % in terms of the number of ancilla inputs and from 17.72 to 91.62 % in terms of the number of garbage outputs. A cost analysis was made for their potential implementation in nanomagnetic logic (NML) computing. It is illustrated that the SCRL gate-based designs of reversible barrel shifters have less NML cost (cost in terms of number of inverters and majority voters) compared to the Fredkin gate-based designs of reversible barrel shifters.


Reversible logic SCRL gate NML computing Barrel shifter 


  1. 1.
    Alam M, Karim M (1992) Programmable optical perfect shuffle interconnection network using fredkin gates. Microw Opt Technol Lett 5(7):330–333CrossRefGoogle Scholar
  2. 2.
    Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17(6):525–532MathSciNetCrossRefzbMATHGoogle Scholar
  3. 3.
    Biswas AK, Hasan MM, Chowdhury AR, Babu HMH (2008) Efficient approaches for designing reversible binary coded decimal adders. Microelectron J 39(12):1693–1703CrossRefGoogle Scholar
  4. 4.
    Brigham EO, Brigham E (1988) The fast Fourier transform and its applications, vol 1. Prentice Hall, Englewood CliffszbMATHGoogle Scholar
  5. 5.
    DeBenedictis EP (2005) Reversible logic for supercomputing. In: Proceedings of the 2nd conference on computing frontiers. ACM, New York, pp 391–402Google Scholar
  6. 6.
    Desoete B, De Vos A (2002) A reversible carry-look-ahead adder using control gates. Integr VLSI J 33(1):89–104CrossRefzbMATHGoogle Scholar
  7. 7.
    Donald J, Jha NK (2008) Reversible logic synthesis with fredkin and peres gates. ACM J Emerg Technol Comput Syst 4(1):2CrossRefGoogle Scholar
  8. 8.
    Golubitsky O, Falconer SM, Maslov D (2010) Synthesis of the optimal 4-bit reversible circuits. In: Proceedings of the 47th design automation conference. ACM, New York, pp 653–656Google Scholar
  9. 9.
    Golubitsky O, Maslov D (2012) A study of optimal 4-bit reversible toffoli circuits and their synthesis. IEEE Trans Computers 61(9):1341–1353MathSciNetCrossRefGoogle Scholar
  10. 10.
    Gupta P, Agrawal A, Jha NK (2006) An algorithm for synthesis of reversible logic circuits. IEEE Trans Computer-Aided Design Integr Circuits Syst 25(11):2317–2330CrossRefGoogle Scholar
  11. 11.
    Haghparast M, Jassbi SJ, Navi K, Hashemipour O (2008) Design of a novel reversible multiplier circuit using HNG gate in nanotechnology. World Appl Sci J (Citeseer) Google Scholar
  12. 12.
    Hosseininia N, Boroumand S, Haghparast M (2015) Novel nanometric reversible low power bidirectional universal logarithmic barrel shifter with overflow and zero flags. J Circuits Syst Computers 24:1550049CrossRefGoogle Scholar
  13. 13.
    Kotiyal S (2012) Design methodologies for reversible logic based barrel shifters. M.S.E.E. Thesis. University of South FloridaGoogle Scholar
  14. 14.
    Landauer R (1961) Irreversibility and heat generation in the computational process. IBM J Res Dev 5:183–191MathSciNetCrossRefzbMATHGoogle Scholar
  15. 15.
    Maslov D, Dueck GW (2004) Reversible cascades with minimal garbage. IEEE Trans Computer-Aided Design Integr Circuits Syst 23(11):1497–1509CrossRefGoogle Scholar
  16. 16.
    Maslov D, Dueck GW, Miller DM (2007) Techniques for the synthesis of reversible toffoli networks. ACM Trans Design Autom Electron Syst 12(4):42CrossRefGoogle Scholar
  17. 17.
    Maslov D, Saeedi M (2011) Reversible circuit optimization via leaving the boolean domain. IEEE Trans Computer-Aided Design Integr Circuits Syst 30(6):806–816CrossRefGoogle Scholar
  18. 18.
    Mitra SK, Chowdhury AR (2015) Optimized logarithmic barrel shifter in reversible logic synthesis. In: 2015 28th international conference on VLSI design (VLSID). IEEE, pp 441–446Google Scholar
  19. 19.
    Nachtigal M, Thapliyal H, Ranganathan N (2011) Design of a reversible floating-point adder architecture. In: 2011 11th IEEE conference on nanotechnology (IEEE-NANO). IEEE, pp 451–456Google Scholar
  20. 20.
    Pillmeier MR, Schulte MJ, Walters III EG (2002) Design alternatives for barrel shifters. In: International symposium on optical science and technology, pp 436–447. International Society for Optics and PhotonicsGoogle Scholar
  21. 21.
    Porod W, Bernstein GH, Csaba G, Hu SX, Nahas J, Niemier MT, Orlov A (2014) Nanomagnet logic (nml). In: Field-coupled nanocomputing. Springer, New York, pp 21–32Google Scholar
  22. 22.
    Rice JE (2008) An introduction to reversible latches. Computer J 51(6):700–709CrossRefGoogle Scholar
  23. 23.
    Shamsujjoha M, Babu HMH, Jamal L, Chowdhury AR (2013) Design of a fault tolerant reversible compact unidirectional barrel shifter. In: 2013 26th International conference on VLSI design and 2013 12th international conference on embedded systems (VLSID). IEEE, pp 103–108Google Scholar
  24. 24.
    Takahashi Y (2009) Quantum arithmetic circuits: a survey. IEICE Trans Fundam Electron Commun Computer Sci 92(5):1276–1283CrossRefGoogle Scholar
  25. 25.
    Takahashi Y, Kunihiro N (2005) A linear-size quantum circuit for addition with no ancillary qubits. Quantum Inf Comput 5(6):440–448MathSciNetzbMATHGoogle Scholar
  26. 26.
    Takahashi Y, Tani S, Kunihiro N (2009) Quantum addition circuits and unbounded fan-out. arXiv:0910.2530
  27. 27.
    Thapliyal H, Arabnia H, Vinod AP (2006) Combined integer and floating point multiplication architecture (cifm) for fpgas and its reversible logic implementation. In: 49th IEEE international midwest symposium on circuits and systems, 2006. MWSCAS’06, vol 2, pp 438–442. IEEEGoogle Scholar
  28. 28.
    Thapliyal H, Arabnia HR (2006) Reversible programmable logic array (rpla) using fredkin & feynman gates for industrial electronics and applications. cs/0609029
  29. 29.
    Thapliyal H, Arabnia HR, Srinivas M (2006) Reduced area low power high throughput bcd adders for ieee 754r format. cs/0609036
  30. 30.
    Thapliyal H, Jayashree H, Nagamani A, Arabnia H (2013) Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder. In: Gavrilova M, Tan C (eds) Transactions on computational science XVII, Lecture notes in computer science, vol 7420, pp 73–97. Springer Berlin HeidelbergGoogle Scholar
  31. 31.
    Thapliyal H, Ranganathan N, Kotiyal S (2014) Reversible logic based design and test of field coupled nanocomputing circuits. In: Field-coupled nanocomputing. Springer, New York, pp 133–172Google Scholar
  32. 32.
    Thapliyal H, Srinivas M, Arabnia HR (2005) Reversible logic synthesis of half, full and parallel subtractors. In: ESA, pp 165–181Google Scholar
  33. 33.
    Thapliyal H, Srinivas MB, Arabnia HR (2005) A need of quantum computing: reversible logic synthesis of parallel binary adder-subtractor. In: Embedded systems and applications, pp 60–68Google Scholar
  34. 34.
    Vacca M (2013) Emerging technologies-nanomagnets logic (nml). Ph.D. thesis, Politecnico di TorinoGoogle Scholar
  35. 35.
    Vacca M, Graziano M, Wang J, Cairo F, Causapruno G, Urgese G, Biroli A, Zamboni M (2014) Nanomagnet logic: an architectural level overview. Lecture Notes in Computer Science, pp 223–256Google Scholar
  36. 36.
    Varga E, Orlov A, Niemier MT, Hu XS, Bernstein GH, Porod W (2010) Experimental demonstration of fanout for nanomagnet logic. IEEE Trans Nanotechnol 9(6):668–670CrossRefGoogle Scholar
  37. 37.
    Yang G, Song X, Hung WN, Perkowski MA (2008) Bi-directional synthesis of 4-bit reversible circuits. Computer J 51(2):207–215CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringUniversity of KentuckyLexingtonUSA

Personalised recommendations