The Journal of Supercomputing

, Volume 71, Issue 7, pp 2720–2747 | Cite as

Latency-aware DVFS for efficient power state transitions on many-core architectures

  • Zhiquan Lai
  • King Tin Lam
  • Cho-Li Wang
  • Jinshu Su
Article

Abstract

Energy efficiency is quickly becoming a first-class design constraint in high-performance computing (HPC). We need more efficient power management solutions to save energy costs and carbon footprint of HPC systems. Dynamic voltage and frequency scaling (DVFS) is a commonly used power management technique for making a trade-off between power consumption and system performance according to the time-varying program behavior. However, prior work on DVFS seldom takes into account the voltage and frequency scaling latencies, which we found to be a crucial factor determining the efficiency of the power management scheme. Frequent power state transitions without latency awareness can make a real impact on the execution performance of applications. The design of multiple voltage domains in some many-core architectures has made the effect of DVFS latencies even more significant. These concerns lead us to propose a new latency-aware DVFS scheme to adjust the optimal power state more accurately. Our main idea is to analyze the latency characteristics in depth and design a novel profile-guided DVFS solution which exploits the varying execution patterns of the parallel program to avoid excessive power state transitions. We implement the solution into a power management library for use by shared-memory parallel applications. Experimental evaluation on the Intel SCC many-core platform shows significant improvement in power efficiency after using our scheme. Compared with a latency-unaware approach, we achieve 24.0 % extra energy saving, 31.3 % more reduction in the energy–delay product and 15.2 % less overhead in execution time in the average case for various benchmarks. Our algorithm is also proved to outperform a prior DVFS approach attempted to mitigate the latency effects.

Keywords

Power management Dynamic voltage and frequency scaling Profiling Shared virtual memory Many-core processors The single-chip cloud computer 

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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Zhiquan Lai
    • 1
  • King Tin Lam
    • 2
  • Cho-Li Wang
    • 2
  • Jinshu Su
    • 1
  1. 1.National Key Laboratory of Parallel and Distributed Processing, College of ComputerNational University of Defense TechnologyChangshaChina
  2. 2.Department of Computer ScienceThe University of Hong KongHong KongChina

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