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The Journal of Supercomputing

, Volume 69, Issue 1, pp 161–199 | Cite as

Improved extra group network: a new fault-tolerant multistage interconnection network

  • Fathollah Bistouni
  • Mohsen Jahanshahi
Article

Abstract

Supersystems are shown to provide enough computational power to solve complex problems on a real-time basis. In all these systems, the computational parallelism is obtained from multiple processors. Multistage interconnection networks (MINs) play a vital role on the performance of these multiprocessor systems. This paper introduces a new fault-tolerant MIN named as improved extra group network (IEGN). IEGN is designed by existing extra group (EGN) network, which is a regular multipath network with limited fault tolerance. IEGN provides four times more paths between any source–destination pairs compared with EGN. The performance of IEGN has been evaluated in terms of permutation capability, fault tolerance, reliability, path length, and cost. It has also been proved that the IEGN can achieve better results in terms of fault tolerance, reliability, path length and cost-effectiveness, in comparison to known networks, namely, EGN, augmented baseline network, augmented shuffle-exchange network, fault-tolerant double tree, Benes network, and Replicated MIN.

Keywords

Parallel processing Multistage interconnection network Fault tolerance Reliability Extra group network 

Abbreviations

IN

Interconnection network

MIN

Multistage interconnection network

IEGN

Improved extra group network

EGN

Extra group network

ABN

Augmented baseline network

ASEN

Augmented shuffle-exchange network

MABN

Modified augmented baseline network

FDOT

Fault-tolerant double tree network

PCT

Perfect connection techniques

BP

Basic path

MP

Main path

AP

Auxiliary path

SE

Switching element

NOBP

Number of basic path

NOAP

Number of auxiliary path

LOMP

Length of main path

LOAP

Length of auxiliary path

LOBP

Length of basic path

PLE

Path length-effectiveness

SC

Switching component

MSFT

Maximum number of switching components failures tolerated

UB

Upper bound

LB

Lower bound

MUX

Multiplexer

DMUX

Demultiplexer

CE

Cost-effectiveness

RBD

Reliability block diagram

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Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Department of Electrical, Computer and Biomedical Engineering, Qazvin BranchIslamic Azad UniversityQazvinIran
  2. 2.Department of Computer Engineering, Central Tehran BranchIslamic Azad UniversityTehranIran

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