The Journal of Supercomputing

, Volume 68, Issue 2, pp 914–934 | Cite as

Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

  • Epifanio Gaona
  • J. Rubén Titos-Gil
  • Juan Fernández
  • Manuel E. Acacio


In the search for new paradigms to simplify multithreaded programming, Transactional Memory (TM) is currently being advocated as a promising alternative to deadlock-prone lock-based synchronization. In this way, future many-core CMP architectures may need to provide hardware support for TM. On the other hand, power dissipation constitutes a first class consideration in multicore processor designs. In this work, we propose Selective Dynamic Serialization (SDS) as a new technique to improve energy consumption without degrading performance in applications with conflicting transactions by avoiding wasted work due to aborted transactions. Our proposal, which is implemented on top of a hardware transactional memory (HTM) system with an eager conflict management policy, detects and serializes conflicting transactions dynamically (at run-time). In its simplest form, in case of conflict, one transaction is allowed to continue whilst the rest are completely stalled. Once the executing transaction has finished, it wakes up several of the stalling transactions. More elaborated implementations of SDS try to delay this behavior until serialization of transactions is profitable, achieving the best trade-off between performance, energy savings and network traffic. SDS implementations differ from each other in the condition that triggers the serialization mode. We have evaluated several SDS schemes using GEMS, a full-system simulator implementing the LogTM-SE Eager–Eager HTM system, and several benchmarks from the STAMP suite. Results for a 16-core CMP show that SDS obtains reductions of 6 % on average in energy consumption (more than 20 % in high contention scenarios) in a wide range of benchmarks without affecting, on average, execution time. At the same time, network traffic level is also reduced by 22 %.


Many-core CMPs Hardware transactional memory Transactions Run-time serialization Energy consumption  Execution time 



This work was supported by the Spanish MINECO, as well as European Commission FEDER funds, under grant “TIN2012-38341-C04-03”. Epifanio Gaona Ramírez is supported by fellowship 09503/FPI/08 from Fundación Séneca, Agencia Regional de Ciencia y Tecnología de la Región de Murcia (II PCTRM).


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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Epifanio Gaona
    • 1
  • J. Rubén Titos-Gil
    • 2
  • Juan Fernández
    • 3
  • Manuel E. Acacio
    • 1
  1. 1.Universidad de MurciaMurciaSpain
  2. 2.Chalmers University of TechnologyGöteborgSweden
  3. 3.Intel Barcelona Research CenterBarcelonaSpain

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