The Journal of Supercomputing

, Volume 68, Issue 1, pp 414–442 | Cite as

Managing power constraints in a single-core scenario through power tokens

  • Juan M. Cebrián
  • Daniel Sánchez
  • Juan L. Aragón
  • Stefanos Kaxiras


Current microprocessors face constant thermal and power-related problems during their everyday use, usually solved by applying a power budget to the processor/core. Dynamic voltage and frequency scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, the continuous increase of leakage power due to technology scaling along with low resolution of DVFS makes it less attractive as a technique to match a predefined power budget as technology goes to deep-submicron. In this paper, we propose the use of microarchitectural techniques to accurately match a power constraint while maximizing the energy-efficiency of the processor. We will predict the processor power dissipation at cycle level (power token throttling) or at a basic block level (basic block level mechanism), using the dissipated power translated into tokens to select between different power-saving microarchitectural techniques. We also introduce a two-level approach in which DVFS acts as a coarse-grain technique to lower the average power dissipation towards the power budget, while microarchitectural techniques focus on removing the numerous power spikes. Experimental results show that the use of power-saving microarchitectural techniques in conjunction with DVFS is up to six times more precise, in terms of total energy consumed over the power budget, than only using DVFS to match a predefined power budget.


Hardware Power management Power budget DVFS  Energy efficiency Power estimation 



This work was supported by the Spanish MEC, MICINN and EU Commission FEDER funds under Grants CSD2006-00046 and TIN2009-14475-C04. Also by the EU-FP7 ICT Project “Embedded Reconfigurable Architecture (ERA)”, contract No. 249059. Finally, the EU-FP7 HiPEAC funded an internship of J.M. Cebrián at U. Uppsala.


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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Juan M. Cebrián
    • 1
  • Daniel Sánchez
    • 1
  • Juan L. Aragón
    • 1
  • Stefanos Kaxiras
    • 2
  1. 1.University of MurciaMurciaSpain
  2. 2.University of UppsalaUppsalaSweden

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