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Improving performance of software transactional memory through contention locality

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Abstract

In this paper, we introduce contention locality in Transactional Memory (TM) which describes the likelihood that a previously aborted transaction conflicts again in the future. We find that conflicts are highly predictable in TMs and we propose two optimization techniques based on contention locality:

The first optimization technique is Speculative Contention Avoidance (SCA). SCA dynamically controls the number of concurrently executing transactions and serializes those transactions that are likely to conflict. As such, SCA reduces contention in TMs and improves performance. The second optimization technique is Adaptive Validation (AV). We show that there is no single validation policy that works well across all applications. AV adjusts validation based on applications’ behavior and improves performance of TMs.

In this paper, SCA and AV are evaluated using Transactional Locking II (TL2) and Stamp v0.9.10 benchmark suite. The evaluation reveals that SCA and AV are effective and improve performance significantly.

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References

  1. 1.

    Dolev S, Hendler D, Suissa A (2008) CAR-STM: scheduling-based collision avoidance and resolution for software transactional memory. In: Proceedings of the twenty-seventh annual ACM symposium on principles of distributed computing, August 2008, pp 125–134

  2. 2.

    Herlihy M, Moss JEB (1993) Transactional memory: architectural support for lock-free data structures. In: Proceedings of the twentieth annual international symposium on computer architecture

  3. 3.

    Dice D, Shalev O, Shavit N (2006) Transactional locking II. In: Proceedings of the 20th international symposium on distributed computing, September 2006, pp 194–208

  4. 4.

    Minh CC, Trautmann M, Chung JW, McDonald A, Bronson N, Casper J, Kozyrakis C, Olukotun K (2007) An effective hybrid transactional memory system with strong isolation guarantees. In: Proceeding of international symposium on computer architecture, June 2007

  5. 5.

    Dragojevic A, Guerraoui R, Singh AV, Singh V (2009) Preventing versus curing: avoiding conflicts in transactional memories. In: Proceedings of the twenty-eighth annual ACM symposium on principles of distributed computing, August 2009, pp 7–16

  6. 6.

    Saha B, Adl-Tabatabai A-R, Hudson RL, Minh CC, Hertzberg B (2006) McRT-STM: a high performance software transactional memory system for a multi-core runtime. In: Proceedings of PPOPP, March 2006, pp 187–197

  7. 7.

    Stone JM, Stone HS, Heidelberger P, Turek J (1993) Multiple reservations and the Oklahoma update. IEEE Parallel Distrib Technol 1:58–71

  8. 8.

    Shavit N, Touitou D (1995) Software transactional memory. In: Proceedings of ACM symposium on principles of distributed computing, August 1995

  9. 9.

    Harris T, Marlow S, Peyton-Jones S, Herlihy M (2005) Composable memory transactions. In: Proceedings of the tenth ACM SIGPLAN symposium on principles and practice of parallel programming, New York, pp 48–60

  10. 10.

    Fraser K (2004) Practical lock-freedom. Technical report UCAM-CL-TR-579, Cambridge University Computer Laboratory, February 2004

  11. 11.

    Yoo RM, Lee H-HS (2008) Adaptive transaction scheduling for transactional memory systems. In: Proceedings of the twentieth annual symposium on parallelism in algorithms and architectures, pp 169–178

  12. 12.

    Bai T, Shen X, Zhang C, Scherer WN, Ding C, Scott ML (2007) A key-based adaptive transactional memory executor. In: Proceedings of the 21st international parallel and distributed processing symposium, Los Alamitos, 2007

  13. 13.

    Lupon M, Magklis G, González A (2010) A dynamically adaptable hardware transactional memory. In: Proceedings of the 43rd international symposium on microarchitecture, Atlanta (USA), December 2010

  14. 14.

    Herlihy M, Luchangco V, Moir M, Scherer W III (2003) Software transactional memory for dynamic-sized data structures. In: Proceedings of PODC, July 2003, pp 92–101

  15. 15.

    Spear MF, Marathe VJ, Scherer WN III, Scott ML (2006) Conflict detection and validation strategies for software transactional memory. In: Proc of the 20th intl symp on distributed computing, Stockholm, Sweden, Sept 2006

  16. 16.

    Harris T, Fraser K (2003) Language support for lightweight transactions. SIGPLAN Not 38(11):388–402

  17. 17.

    Vallejo E, Harris T, Cristal A, Unsal O, Valero M (2008) Hybrid transactional memory to accelerate safe lock-based transactions. In: Workshop on transactional computing (TRANSACT)

  18. 18.

    Damron P, Fedorova A, Lev Y, Luchangco V, Moir M, Nussbaum D (2006) Hybrid transactional memory. In: Proceedings of the 12th intl. conference on architectural support for programming languages and operating systems, San Jose, CA, Oct 2006

  19. 19.

    Marathe VJ, Spear MF, Heriot C, Acharya A, Eisenstat D, Scherer WN III, Scott ML (2006) Lowering the overhead of nonblocking software transactional memory. In: First ACM SIGPLAN workshop on languages, compilers, and hardware support for transactional computing, June 2006

  20. 20.

    Blundell C, Devietti J, Lewis EL, Martin MMK (2007) Making the fast case common and the uncommon case simple in unbounded transactional memory. In: Proceedings of the 34th annual international symposium on computer architecture, pp 23–34

  21. 21.

    Bobba J, Goyal N, Hill MD, Swift MM, Wood DA, Token TM (2008) Efficient execution of large transactions with hardware transactional memory. In: Proceedings of the 35th international symposium on computer architecture, pp 127–138

  22. 22.

    Culler DE, Singh JP, Gupta A (1998) Parallel computer architecture: a hardware/software approach. Morgan Kaufmann, San Mateo

  23. 23.

    Olukotun K, Hammond L (2005) The future of microprocessors. In: ACM QUEUE magazine, September 2005

  24. 24.

    Ansari M, Luján M, Kotselidis C, Jarvis K, Kirkham CC, Watson I (2009) Steal-on-abort: improving transactional memory performance through dynamic transaction reordering. In: High performance embedded architectures and compilers, fourth international conference (HiPEAC), pp 4–18

  25. 25.

    Marathe VJ, Scherer WN III, Scott ML (2005) Adaptive software transactional memory. In: Proc of the 19th intl symp on distributed computing, Cracow, Poland, Sept 2005

  26. 26.

    Yeh T-Y, Patt Y (1992) Alternative implementations of two-level adaptive branch prediction. In: Proceedings of the 19th annual international symposium on computer architecture, May 1992

  27. 27.

    Dijkstra EW (1968) The structure of the THE multiprogramming system. Commun ACM 11(5):341–346

  28. 28.

    He Z, Yu X, Hong B (2012) Profiling-based adaptive contention management for software transactional memory. In: 26th IEEE international parallel and distributed processing symposium (IPDPS 2012), May 2012

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Correspondence to Ehsan Atoofian.

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Atoofian, E. Improving performance of software transactional memory through contention locality. J Supercomput 64, 527–547 (2013). https://doi.org/10.1007/s11227-012-0854-y

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Keywords

  • Transactional memory
  • Contention locality
  • Performance