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Improving performance of multi-core NUCA coherent systems using NoC-assisted mechanisms

Abstract

The significant speed-gap between processor and memory makes last-level cache performance crucial for multi-core architectures (MCA). Non-uniform cache architecture (NUCA) has been proposed to overcome the performance limitations of MCA for many embedded applications. The cache is partitioned into sub-banks, with each sub-bank being an independently accessible entity connected with a fast on-chip network (NoC). This paper presents two NoC-assisted mechanisms to improve the performance and power consumption of NUCA coherence. The first mechanism provides priority-based communication based on the wormhole routing architecture to support NUCA coherence. High-priority coherent packets are transmitted first to save time. The second mechanism offers multicasting communication based on the proposed priority-based NoC to provide efficient cache coherency for NUCA. We dispatch and collect coherence packets at the collecting nodes (CN) to further decrease the number of coherent messages flowing in the NoC. Experimental results show that the priority-based transmission can improve performance by approximately 10 %. The proposed multicasting mechanism can further improve performance and decrease power consumption of the NoC in NUCA by approximately 15 %. The two proposed mechanisms can together enhance the performance by 25 % averagely.

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Correspondence to Kuei-Chung Chang.

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Chang, K., Liao, I. & Liao, C. Improving performance of multi-core NUCA coherent systems using NoC-assisted mechanisms. J Supercomput 62, 1318–1337 (2012). https://doi.org/10.1007/s11227-012-0793-7

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Keywords

  • Many-core SoC
  • Non-uniform cache architecture
  • Network-on-chip