Applying ROBDDs for Logical Circuit Delay Testing
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Increasing frequency of functioning and decreasing transistor sizes in high performance logical circuits may result in illegal capacities, inductivities, resistances, and so on that generate decreasing estimated circuit frequency. These defects cannot be detected by physical methods. The main way of solving the problem is based on delay testing of logical circuits within the path delay fault (PDF) model. In this paper, facilities of enhancing PDF test sequence quality based on application of Reduced Ordered Binary Decision Diagrams (ROBDDs) that compactly represent all test pairs of neighbor test patterns for the circuit path are studied. Test patterns (Boolean vectors) are neighbor if they differ by only one component. It is established that using of these ROBDDs cut the lengths of test sequences by more than 1/3 in comparison with traditional scan test sequences simultaneously enhancing test sequence quality. In particular, we derive test sequences for robust testable PDFs of sequential circuits decreasing their power consumption and peak power values.
Keywordscombinational and sequential circuits Reduced Ordered Binary Decision Diagram (ROBDD) Disjoint Sum of Product (DSoP) Equivalent Normal Form (ENF) robust testable path delay fault (robust testable PDF)
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