An optimized quantum circuit for converting from sign–magnitude to two’s complement

  • F. OrtsEmail author
  • G. Ortega
  • E. M. Garzón


Nowadays, one of the critical issues to implement quantum algorithms is the required number of elementary gates, qubits and delay. Current quantum computers and simulators are mainly prototypes, and there is a lack of computational resources. Therefore, it is necessary to optimize the quantum operations to reduce the necessary number of gates and qubits. This work presents a novel reversible circuit which is able to convert signed binary numbers to two’s complement of N digits in a quantum environment. The depth of the circuit is O(log N). It is based on the fastest out-of-place carry look-ahead addition quantum circuit currently available. This addition circuit has been adapted to make the conversion using the minimum number of gates and qubits, being faster than other adder circuits. A robust metric has been used to measure the quantum cost, delay, ancilla inputs and garbage outputs of the proposed converter. Moreover, it has been compared with others described in the literature.


Quantum computation Quantum circuit Reversible circuit Two’s complement Sign–magnitude representation to two’s complement converter 



This work has been partially supported by the Spanish Ministry of Science throughout Project RTI2018-095993-BI00, by J. Andalucía through Project P12-TIC301 and by the European Regional Development Fund (ERDF). F. Orts is supported by an FPI Fellowship (attached to Project TIN2015-66680-C2-1-R) from the Spanish Ministry of Education. The authors wish to thank N.C. Cruz for his valuable support.


  1. 1.
    Baugh, C.R., Wooley, B.A.: A two’s complement parallel array multiplication algorithm. IEEE Trans. Comput. 100(12), 1045–1047 (1973)CrossRefGoogle Scholar
  2. 2.
    Chaudhuri, A., Sultana, M., Sengupta, D., Chaudhuri, A.: A novel reversible two’s complement gate (TCG) and its quantum mapping. In: Devices for Integrated Circuit (DevIC), 2017, pp. 252–256. IEEE (2017)Google Scholar
  3. 3.
    Chaudhuri, A., Sultana, M., Sengupta, D., Chaudhuri, C., Chaudhuri, A.: A reversible approach to two’s complement addition using a novel reversible TCG gate and its 4 dot 2 electron QCA architecture. Microsyst. Technol. 25(5), 1965–1975 (2019)CrossRefGoogle Scholar
  4. 4.
    Cho, H., Swartzlander Jr., E.E.: Adder and multiplier design in quantum-dot cellular automata. IEEE Trans. Comput. 58(6), 721–727 (2009)MathSciNetCrossRefGoogle Scholar
  5. 5.
    Cuccaro, S.A., Draper, T.G., Kutin, S.A., Moulton, D.P.: A new quantum ripple-carry addition circuit (2004). arXiv preprint arXiv:quant-ph/0410184
  6. 6.
    Draper, T.G., Kutin, S.A., Rains, E.M., Svore, K.M.: A logarithmic-depth quantum carry look-ahead adder (2004). arXiv preprint arXiv:quant-ph/0406142
  7. 7.
    Gupta, A., Singla, P., Gupta, J., Maheshwari, N.: An improved structure of reversible adder and subtractor (2013). arXiv preprint arXiv:1306.1889
  8. 8.
    Haghparast, M., Jassbi, S.J., Navi, K., Hashemipour, O.: Design of a novel reversible multiplier circuit using hng gate in nanotechnology. In: World Appl. Sci. J. Citeseer (2008)Google Scholar
  9. 9.
    Hung, W.N., Song, X., Yang, G., Yang, J., Perkowski, M.: Optimal synthesis of multiple output boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9), 1652–1663 (2006)CrossRefGoogle Scholar
  10. 10.
    Islam, M.S., Rahman, M.M., Begum, Z., Hafiz, M.Z.: Fault tolerant reversible logic synthesis: carry look-ahead and carry-skip adders. In: International Conference on Advances in Computational Tools for Engineering Applications, 2009 (ACTEA’09). pp. 396–401. IEEE (2009)Google Scholar
  11. 11.
    Khosropour, A., Aghababa, H., Forouzandeh, B.: Quantum division circuit based on restoring division algorithm. In: 2011 Eighth International Conference on Information Technology: New Generations, pp. 1037–1040. IEEE (2011)Google Scholar
  12. 12.
    Kianpour, M., Sabbaghi-Nadooshan, R.: Novel 8-bit reversible full adder/subtractor using a QCA reversible gate. J. Comput. Electron. 16(2), 459–472 (2017)CrossRefGoogle Scholar
  13. 13.
    Koren, I.: Computer Arithmetic Algorithms. AK Peters/CRC Press, Boca Raton (2001)zbMATHGoogle Scholar
  14. 14.
    Lanyon, B.P., Barbieri, M., Almeida, M.P., Jennewein, T., Ralph, T.C., Resch, K.J., Pryde, G.J., O’Brien, J.L., Gilchrist, A., White, A.G.: Simplifying quantum logic using higher-dimensional Hilbert spaces. Nat. Phys. 5(2), 134–140 (2009)CrossRefGoogle Scholar
  15. 15.
    Lemr, K., Bartkiewicz, K., Cernoch, A., Duek, M., Soubusta, J.: Experimental implementation of optimal linear-optical controlled-unitary gates. Phys. Rev. Lett. 114(15), 153602 (2015)ADSCrossRefGoogle Scholar
  16. 16.
    Li, R., Alvarez-Rodriguez, U., Lamata, L., Solano, E.: Approximate quantum adders with genetic algorithms: an IBM quantum experience. Quantum Meas. Quantum Metrol. 4(1), 1–7 (2017)ADSCrossRefGoogle Scholar
  17. 17.
    Ling, H.: High-speed binary adder. IBM J. Res. Dev. 25(3), 156–166 (1981)MathSciNetCrossRefGoogle Scholar
  18. 18.
    Lisa, N.J., Babu, H.M.H.: Design of a compact reversible carry look-ahead adder using dynamic programming. In: 2015 28th International Conference on VLSI Design (VLSID), pp. 238–243. IEEE (2015)Google Scholar
  19. 19.
    Markov, I.L., Saeedi, M.: Constant-optimized quantum circuits for modular multiplication and exponentiation (2012). arXiv preprint arXiv:1202.6614
  20. 20.
    Mazumder, M.: Synthesis of quantum circuit for full adder using khan gate. Int. J. Appl. Inn. Eng. Manag. (IJAIEM) 6(6), 226–232 (2017)MathSciNetGoogle Scholar
  21. 21.
    Moghimi, S., Reshadinezhad, M.R.: A novel 4\(\times 4 \) universal reversible gate as a cost efficient full adder/subtractor in terms of reversible and quantum metrics. Int. J. Mod. Educ. Comput. Sci. 7(11), 28–34 (2015)Google Scholar
  22. 22.
    Mohammadi, M., Eshghi, M.: On figures of merit in reversible and quantum logic designs. Quantum Inf. Process. 8(4), 297–318 (2009)MathSciNetCrossRefGoogle Scholar
  23. 23.
    Mokhtari, D., Rezai, A., Rashidi, H., Rabiei, F., Emadi, S., Karimi, A.: Design of novel efficient full adder architecture for quantum-dot cellular automata technology. Facta Universitatis, Series: Electronics and Energetics 31(2), 279–285 (2018)Google Scholar
  24. 24.
    Montaser, R., Younes, A., Abdel-Aty, M.: New design of reversible full adder/subtractor using \( r \) gate (2017). arXiv preprint arXiv:1708.00306
  25. 25.
    Murali, K., Sinha, N., Mahesh, T., Levitt, M.H., Ramanathan, K., Kumar, A.: Quantum-information processing by nuclear magnetic resonance: experimental implementation of half-adder and subtractor operations using an oriented spin-7/2 system. Phys. Rev. A 66(2), 022313 (2002)ADSCrossRefGoogle Scholar
  26. 26.
    Nielsen, M.A., Chuang, I.L.: Quantum Computation and Quantum Information, 10th edn. Cambridge University Press, Cambridge (2017)zbMATHGoogle Scholar
  27. 27.
    Orts, F., Ortega, G., Garzón, E.M.: A quantum circuit for solving divisions using Grover’s search algorithm. In: Proceedings of 18th International Conference on Computational and Mathematical Methods in Science and Engineering (2018)Google Scholar
  28. 28.
    Orts, F., Ortega, G., Garzón, E.M.: A faster half subtractor circuit using reversible quantum gates. Baltic J. Mod. Comput. 7(1), 99–111 (2019)CrossRefGoogle Scholar
  29. 29.
    Rahmati, M., Houshmand, M., Kaffashian, M.H.: Novel designs of a carry/borrow look-ahead adder/subtractor using reversible gates. J. Comput. Electron. 16(3), 856–866 (2017)CrossRefGoogle Scholar
  30. 30.
    Shukla, V., Singh, O., Mishra, G., Tiwari, R.: Design of a 4-bit 2’s complement reversible circuit for arithmetic logic unit applications. In: The International Conference on Communication, Computing and Information Technology (ICCCMIT), Special Issue of International Journal of Computer Applications, pp. 1–5 (2012)Google Scholar
  31. 31.
    Takahashi, Y., Kunihiro, N.: A linear-size quantum circuit for addition with no ancillary qubits. Quantum Inf. Comput. 5(6), 440–448 (2005)MathSciNetzbMATHGoogle Scholar
  32. 32.
    Takahashi, Y., Kunihiro, N.: A fast quantum circuit for addition with few qubits. Quantum Inf. Comput. 8(6), 636–649 (2008)MathSciNetzbMATHGoogle Scholar
  33. 33.
    Takahashi, Y., Tani, S., Kunihiro, N.: Quantum addition circuits and unbounded fan-out. Quantum Inf. Comput. 10(9), 872–890 (2010)MathSciNetzbMATHGoogle Scholar
  34. 34.
    Talib, G.H.B., El-Maleh, A.H., Sait, S.M.: Design of fault tolerant adders: a review. Arab. J. Sci. Eng. 43(12), 6667–6692 (2018)CrossRefGoogle Scholar
  35. 35.
    Thapliyal, H.: Mapping of subtractor and adder-subtractor circuits on reversible quantum gates. In: Transactions on Computational Science XXVII, pp. 10–34. Springer (2016)Google Scholar
  36. 36.
    Thapliyal, H., Jayashree, H., Nagamani, A., Arabnia, H.R.: Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder. In: Transactions on Computational Science XVII, pp. 73–97. Springer (2013)Google Scholar
  37. 37.
    Theresal, T., Sathish, K., Aswinkumar, R.: A new design of optical reversible adder and subtractor using mzi. Int. J. Sci. Res. Publ. (IJSRP) 5(4) (2015)Google Scholar
  38. 38.
    Toffoli, T.: Reversible computing. In: International Colloquium on Automata, Languages, and Programming, pp. 632–644. Springer (1980)Google Scholar
  39. 39.
    Wang, F., Luo, M., Li, H., Qu, Z., Wang, X.: Improved quantum ripple-carry addition circuit. Sci. China Inf. Sci. 59, 042406 (2016)CrossRefGoogle Scholar
  40. 40.
    Wang, J., Choi, K.: A carry look-ahead adder designed by reversible logic. In: SoC Design Conference (ISOCC), 2014 International, pp. 216–217. IEEE (2014)Google Scholar
  41. 41.
    Williams, C.P.: Explorations in quantum computing. Springer, Berlin (2010)zbMATHGoogle Scholar

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Authors and Affiliations

  1. 1.Informatics DepartmentUniversity of Almería, ceiA3AlmeríaSpain
  2. 2.Computer Architecture Department, Campus TeatinosUniversity of MálagaMálagaSpain

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