Quantum circuit design for objective function maximization in gatemodel quantum computers
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Abstract
Gatemodel quantum computers provide an experimentally implementable architecture for nearterm quantum computations. To design a reduced quantum circuit that can simulate a highcomplexity reference quantum circuit, an optimization should be taken on the number of input quantum states, on the unitary operations of the quantum circuit, and on the number of output measurement rounds. Besides the optimization of the physical layout of the hardware layer, the quantum computer should also solve difficult computational problems very efficiently. To yield a desired output system, a particular objective function associated with the computational problem fed into the quantum computer should be maximized. The reduced gate structure should be able to produce the maximized value of the objective function. These parallel requirements must be satisfied simultaneously, which makes the optimization difficult. Here, we demonstrate a method for designing quantum circuits for gatemodel quantum computers and define the Quantum Triple Annealing Minimization (QTAM) algorithm. The aim of QTAM is to determine an optimal reduced topology for the quantum circuits in the hardware layer at the maximization of the objective function of an arbitrary computational problem.
Keywords
Quantum computations Quantum computers Gatemodel quantum computers1 Introduction
According to Moore’s law [1], traditional computer architectures will reach their physical limits in the near future. Quantum computers [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] provide a tool to solve problems more efficiently than ever would be possible with traditional computers [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16]. The power of quantum computing is based on the fundamentals of quantum mechanics. In a quantum computer, information is represented by quantum information, and information processing is achieved by quantum gates that realize quantum operations [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 25, 26]. These quantum operations are performed on the quantum states, which are then outputted and measured in a measurement phase. The measurement process is applied to each quantum state where the quantum information conveyed by the quantum states is converted into classical bits. Quantum computers have been demonstrated in practice [2, 3, 4, 5, 6, 7, 8, 9], and several implementations are currently in progress [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 20].
In the physical layer of a gatemodel quantum computer, the device contains quantum gates, quantum ports (of quantum gates), and quantum wires for the quantum circuit. (Note: The term quantum circuit, in general, refers to software, not hardware; it is a description or prescription for what quantum operations should be applied and when and does not refer to a physically implemented circuit analogous to a printed electronic circuit. In our setting, it refers to the hardware layer.) In contrast to traditional automated circuit design [27, 28, 29, 30, 31, 32, 33], a quantum system cannot participate in more than one quantum gate simultaneously. As a corollary, the quantum gates of a quantum circuit are applied in several rounds in the physical layer of the quantum circuit [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 20].
The physical layout design and optimization of quantum circuits have different requirements with several open questions and currently represent an active area of study [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16, 17, 18, 19, 20]. Assuming that the goal is to construct a reduced quantum circuit that can simulate the original system, the reduction process should be taken on the number of input quantum states, gate operations of the quantum circuit, and the number of output measurements. Another important question is the maximization of objective function associated with an arbitrary computational problem that is fed into the quantum computer. These parallel requirements must be satisfied simultaneously, which makes the optimization procedure difficult and is an emerging issue in present and future quantum computer developments.
In the proposed QTAM method, the goal is to determine a topology for the quantum circuits of quantum computer architectures that can solve arbitrary computational problems such that the quantum circuit is minimized in the physical layer, and the objective function of an arbitrary selected computational problem is maximized. The physical layer minimization covers the simultaneous minimization of the quantum circuit area (quantum circuit height and depth of the quantum gate structure, where the depth refers to the number of time steps required for the quantum operations making up the circuit to be run on quantum hardware), the total area of the quantum wires of the quantum circuit, the maximization of the objective function, and the minimization of the required number of input quantum systems and output measurements. An important aim of the physical layout minimization is that the resulting quantum circuit should be identical to a highcomplexity reference quantum circuit (i.e., the reduced quantum circuit should be able to simulate a nonreduced quantum circuit).
The minimization of the total quantum wire length in the physical layout is also an objective in QTAM. It serves to improve the processing in the topology of the quantum circuit. However, besides the minimization of the physical layout of the quantum circuit, the quantum computer also has to solve difficult computational problems very efficiently (such as the maximization of an arbitrary combinatorial optimization objective function [17, 18, 19, 20]). To achieve this goal in the QTAM method, we also defined an objective function that provides the maximization of objective functions of arbitrary computational problems. The optimization method can be further tuned by specific input constraints on the topology of the quantum circuit (paths in the quantum circuit, organization of quantum gates, required number of rounds of quantum gates, required number of measurement operators, Hamiltonian minimization, entanglement between quantum states, etc.) or other hardware restrictions of quantum computers, such as the wellknown nocloning theorem [23]. The various restrictions on quantum hardware, such as the number of rounds required to be integrated into the quantum gate structure, or entanglement generation between the quantum states is included in the scheme. These constraints and design attributes can be handled in the scheme through the definition of arbitrary constraints on the topology of the quantum circuit or by constraints on the computational paths.
The combinatorial objective function is measured on a computational basis, and an objective function value is determined from the measurement result to quantify the current state of the quantum computer. Quantum computers can be used for combinatorial optimization problems. These procedures aim to use the quantum computer to produce a quantum system that is dominated by computational basis states such that a particular objective function is maximized.
Recent experimental realizations of quantum computers are qubit architectures [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20], and the current quantum hardware approaches focus on qubit systems (i.e., the dimension d of the quantum system is two, \(d=2\)). However, while the qubit layout is straightforwardly inspirable by ongoing experiments, the method is developed for arbitrary dimensions to make it applicable for future implementations. Motivated by these assumptions, we therefore would avoid the term ‘qubit’ in our scheme to address the quantum states and instead use the generalized term, ‘quantum states’ throughout, which refers to an arbitrarydimensional quantum system. We also illustrate the results through superconducting quantum circuits [2, 3, 4, 5, 6]; however, the framework is general and flexible, allowing a realization for nearterm gatemodel quantum computer implementations.

We define a method for designing quantum circuits for gatemodel quantum computers.

We conceive the QTAM algorithm, which provides a quantum circuit minimization on the physical layout (circuit depth and area), quantum wire length minimization, objective function maximization, input size and measurement size minimization for quantum circuits.

We define a multilayer structure for quantum computations using the hardware restrictions on the topology of gatemodel quantum computers.
2 Related works
The related works are summarized as follows.
A strong theoretical background on the logical model of gatemodel quantum computers can be found in [17, 18, 19]. In [16], the model of a gatemodel quantum neural network model is defined. The gatemodel quantum neural network refers to a quantum neural network implemented on gatemodel quantum computers.
In [34], the authors defined a hierarchical approach to computeraided design of quantum circuits. The proposed model was designed for the synthesis of permutation class of quantum logic circuits. The method integrates evolutionary and genetic approaches to evolve arbitrary quantum circuit specified by a target unitary matrix. Instead of circuit optimization, the work focuses on circuit synthesis.
In [35], the authors propose a simulation of quantum circuits by lowrank stabilizer decompositions. The work focuses on the problem of simulation of quantum circuits containing a few nonClifford gates. The framework focuses on the theoretical description of the stabilizer rank. The authors also derived the simulation cost.
A method for the designing of a Tcount optimized quantum circuit for integer multiplication with \(4n+1\) qubits was defined in [36]. The Tcount [37] measures the number of Tgates and has relevance because of the implementation cost of a Tgate is high. The aim of the Tcount optimization is to reduce the number of Tgates without substantially increasing the number of qubits. The method also applied for quantum circuit designs of integer division [38]. The optimization takes into consideration both the Tcount and Tdepth, since Tdepth is also an important performance measure to reduce the implementation costs. Another method for designing of reversible floating point divider units was proposed in [39].
In [40], a methodology for quantum logic gate construction was defined. The main purpose of the scheme was to construct faulttolerant quantum logic gates with a simple technique. The method is based on the quantum teleportation method [41].
A method for the synthesis of depthoptimal quantum circuits was defined in [42]. The aim of the proposed algorithm is to compute the depthoptimal decompositions of logical operations via an application of the socalled meetinthemiddle technique. The authors also applied their scheme for the factorizations of some quantum logical operations into elementary gates in the Clifford+T set.
A framework to the study the compilation and description of faulttolerant, highlevel quantum circuits is proposed in [43]. The authors defined a method to convert highlevel quantum circuits consisting of commonly used gates into a form employing all decompositions and ancillary protocols needed for faulttolerant error correction. The method also represents a useful tool for quantum hardware architectures with topological quantum codes.
An optimization algorithm for quantum computers is defined in [18]. The optimization algorithm is called Quantum Approximate Optimization Algorithm (QAOA). The goal of QAOA is to output approximate solutions for combinatorial optimization problems fed into the quantum computer. The algorithm is implementable via gatemodel quantum computers. It also has been found in this work that the depth of the quantum circuit grows linearly with a particular control parameter. The authors also studied the performance of the algorithm in function of the control parameters.
In [44], the authors studied the attributes of the QAOA algorithm. As they concluded, at some particular setting and conditions the objective function values could become concentrated. As a result, the number of running sequences of the quantum computer can be reduced.
In [45], the authors analyzed the performance, working mechanism, and the experimental implementation of the QAOA algorithm on nearterm gatemodel quantum devices. The work also defined a parameter optimization procedure for the QAOA and evaluated the performance of QAOA and compared it with quantum annealing. As the authors found, the QAOA can learn via optimization to utilize nonadiabatic mechanisms.
The implementation of QAOA with parallelizable gates is studied in [46]. The work defines a scheme to parallelize the QAOA for arbitrary alltoall connected problem graphs in a layout of qubits. The proposed method is defined by singlequbit operations, and the interactions are set by pairwise CNOT gates among nearest neighbors. As the work concluded, this structure allows for a parallelizable implementation in quantum devices with a square lattice geometry.
In [47], the performance of QAOA is studied on different problems. The analysis covers the MaxCut combinatorial optimization problem and the problem of quantum circuit optimizations on a classical computer using automatic differentiation and stochastic gradient descent. The work also revealed that QAOA can exceed the performance of a classical polynomial time algorithm (Goemans–Williamson algorithm [48]) with modest circuit depth. The work also concluded that the performance of QAOA with fixed circuit depth is insensitive to problem size.
In [49], the authors studied the problem of ultrafast state preparation via the QAOA with longrange interactions. The works provide an application for the QAOA in nearterm gatemodel quantum devices. As the authors concluded, the QAOAbased approach leads to an extremely efficient state preparation, for example the method allows us to prepare Greene–Horne–Zeilinger (GHZ) states with \(\mathcal {O}\left( 1 \right) \) circuit depth. The results were also demonstrated by several other examples.
Another experimental approach for the implementation of qubit entanglement and parallel logic operations with a superconducting circuit was presented in [50]. In this work, the authors generated entangled GHZ states with up to 10 qubits connecting to a bus resonator in a superconducting circuit. In the proposed implementation, the resonatormediated qubit–qubit interactions are used to control the entanglement between the qubits and to operate on different pairs in parallel.
A review on the noisy intermediatescale quantum (NISQ) era and its technological effects and impacts on quantum computing can be found in [51].
The subject of quantum computational supremacy (tasks and problems that quantum computers can solve but are beyond the capability of any classical computer) and its practical implications are discussed in [52]. For a work on the complexitytheoretic foundations of quantum supremacy, see [53].
A comprehensive survey on quantum channels can be found in [11], while for a survey on quantum computing technology, see [54].
3 System model
The simultaneous physical layer minimization and the maximization of the objective function are achieved by the Quantum Triple Annealing Minimization (QTAM) algorithm. The QTAM algorithm utilizes the framework of simulated annealing (SA) [27, 28, 29, 30, 31, 32, 33], which is a stochastic pointtopoint search method.
3.1 Computational model
Since SA is a probabilistic procedure it is important to minimize the acceptance probability of unfavorable solutions and avoid getting stuck in a local minima.
3.2 Objective functions
3.3 Constraint violations
The optimization at several different objective functions results in different Pareto fronts [27, 28, 29, 30] of placements of quantum gates in the physical layout. These Pareto fronts allow us to find feasible tradeoffs between the optimization objectives of the QTAM method. The optimization process includes diverse objective functions, constraints, and optimization criteria to improve the performance of the quantum circuit and to take into consideration the hardware restrictions of quantum computers. In the proposed QTAM algorithm, the constraints are endorsed by the modification of the Pareto dominance [27, 28, 29, 30] values by the different sums of constraint violation values. We defined three different constraint violation values.
3.3.1 Distribution closeness dominance
In the QTAM algorithm, the Pareto dominance is first modified with the sum of distribution closeness violation values, denoted by \(c_{s} \left( \cdot \right) \). The aim of this iteration is to support the closeness of output distributions of the reduced quantum circuit QG to the output distribution of the reference quantum circuit \(QG_{R} \).
3.3.2 Constraint dominance
3.3.3 Objective dominance
3.4 Objective function maximization
In \(G_{QG}^{k,r} \) different unitary operations can be defined for the single quantum ports (qubits) and the connected quantum ports, as follows.
The maximization of objective function (24) in the multilayer \(G_{QG}^{k,r} \) structure is therefore analogous to the problem of finding the parameters of sets \({{\mathcal {S}}}_{\vec {\mu }}^{u} \) (38) and \({{\mathcal {S}}}_{\vec {\gamma }}^{u} \) (39) in the system state \(\left \phi \right\rangle \) (40) of the QG quantum circuit.
3.5 The QTAM algorithm
Theorem 1
The QTAM algorithm utilizes annealing temperatures \(T_{f} \left( t\right) \), \(T_{g} \left( t\right) \) and \(T_{c} \left( t\right) \) to evaluate the acceptance probabilities, where \(T_{f} \left( t\right) \) is the annealing temperature for the objectives, \(T_{g} \left( t\right) \) is the annealing temperature for the constraints, and \(T_{c} \left( t\right) \) is the annealing temperature for the distribution closeness.
Proof
3.5.1 Computational complexity of QTAM
4 Wiring optimization and objective function maximization
4.1 Multilayer quantum circuit grid
An ith quantum gate of QG is denoted by \(g_{i} \), a kth port of the quantum gate \(g_{i} \) is referred to as \(g_{i,k} \). Due to the hardware restrictions of gatemodel quantum computer implementations [17, 18, 19, 20], the quantum gates are applied in several rounds. Thus, a multilayer, kdimensional (for simplicity we assume \(k=2\)), nsized finite squarelattice grid \(G_{QG}^{k,r} \) can be constructed for QG, where r is the number of layers, \(l_{z} \), \(z=1,\ldots ,r\) . A quantum gate \(g_{i} \) in the zth layer \(l_{z} \) is referred to as \(g_{i}^{l_{z} } \), while a kth port of \(g_{i}^{l_{z} } \) is referred to as \(g_{i,k}^{l_{z} } \).
4.2 Method
Theorem 2
There exists a method for the parallel optimization of quantum wiring in physical layout of the quantum circuit and for the maximization of an objective function \(C_{\alpha } \left( z\right) \).
Proof
The aim of this procedure (Method 1) is to provide a simultaneous physical layer optimization and Hamiltonian minimization via the minimization of the wiring lengths in the multilayer structure of QG and the maximization of the objective function (see also Sect. 3.4). Formally, the aim of Method 1 is the \(F_{{2}} \wedge F_{{3}} \) simultaneous realization of the objective functions \(F_{{2}} \) and \(F_{{3}} \).
4.3 Quantum circuit minimization
4.3.1 Quantum wire area minimization
In all quantum ports of a particular net k of QG, the source quantum ports are denoted by positive sign [27, 28, 29] in the condensate wave function amplitude, \(\psi _{ij} \) assigned to quantum wire ij between quantum ports i and j, while the sink ports are depicted by negative sign in the condensate wave function amplitude, \(\psi _{ij} \) with respect to a quantum wire ij between quantum ports i and j.
Thus the aim of \(w_{QG} \left( k\right) \) in (70) is to determine a set of porttoport connections in the QG quantum circuit, such that the number of long connections is reduced in a particular net k of QG as much as possible. The result in (71) therefore extends these requirements for all nets of QG.
By some fundamental assumptions, the \({{\mathcal {N}}}_{R} \) residual network of QG is therefore a network of the quantum circuit with forward edges for the increment of the wave function amplitude \(\psi \) and backward edges for the decrement of \(\psi \). To avoid the problem of negative wire lengths, the Bellman–Ford algorithm [27, 28, 29] can be utilized in an iterative manner in the residual directed graph of the QG topology.
To find a path between all pairs of quantum gates in the directed graph of the QG quantum circuit, the directed graph has to be strongly connected. The strong connectivity of the h nets with the parallel minimization of the connections of the QG topology can be achieved by a minimum spanning tree method such as Kruskal’s algorithm [27, 28, 29].
Lemma 1
The objective function \(F_{{2}} \) is feasible in a multilayer QG quantum circuit structure. \(\square \)
Proof
4.3.2 Processing in the multilayer structure
The \(G_{QG}^{k,z} \) grid consists of all \(g_{i} \) quantum gates of QG in a multilayer structure, such that the \(g_{i,k}^{l_{z} } \) appropriate ports of the quantum gates are associated via an directed graph \(\mathrm{\mathrm{G}}=\left( V,E,f_{c} \right) \), where V is the set of ports, \(g_{i,k}^{l_{z} } \subseteq V\), E is the set of edges, and \(f_{c} \) is a cost function, to achieve the gatetogate connectivity.
As a hardware restriction, we use a constraint on the quantum gate structure, and it is assumed in the model that a given quantum system cannot participate in more than one quantum gate at a particular time.
Algorithm
Theorem 3
The Quantum Shortest Path Algorithm finds shortest paths in a multilayer QG quantum circuit structure.
Proof
Complexity analysis The complexity analysis of Algorithm 2 is as follows. Since the QSPA algorithm (Algorithm 2) is based on the \(A^{{*}} \) search method [27, 28, 29], the complexity is trivially yielded by the complexity of the \(A^{{*}} \) search algorithm.
5 Performance evaluation
In this section, we compare the performance of the proposed QTAM method with a multiobjective evolutionary algorithm called NSGAII [55]. We selected this multiobjective evolutionary algorithm for the comparison, since the method can be adjusted for circuit designing.
The computational complexity of NSGAII is proven to be \({{\mathcal {O}}}\left( N_{it} N_{obj} \left {{\mathcal {P}}}\right ^{2} \right) \) in general, while at an optimized nondominated procedure, the complexity can be reduced to \({{\mathcal {O}}}\left( N_{it} N_{obj} \left {{\mathcal {P}}}\right \log _{2} \left {{\mathcal {P}}}\right \right) \). We take into consideration both situations for a comparison. The complexity of QTAM is given in (54).
The complexity of the methods in terms of the number of iterations, \(N_{O}\), is compared in Fig. 4. The performance of QTAM is depicted in Fig. 4a, while b, c illustrate the performances of the NSGAII and optimized NSGAII, respectively.
In the analyzed range, the maximized values of \(N_{O} \) are \(N_{O} \left( \mathrm{QTAM}\right) \approx 2\cdot 10^{6} \), \(N_{O} (\text {NSGAII})\approx 1.25\cdot 10^{8} \), and for the optimized NSGAII scenario, \(N'_{O} \left( {\text {NSGAII}}\right) \approx 2.25\cdot 10^{6} \), respectively. In comparison with NSGAII, the complexity of QTAM is significantly lower. Note, while the performance of QTAM and the optimized NSGAII is closer, QTAM requires no any optimization of the complexity of the nondominated procedure.
6 Conclusions
The algorithms and methods presented here provide a framework for quantum circuit designs for nearterm gatemodel quantum computers. Since our aim was to define a scheme for present and future quantum computers, the developed algorithms and methods were tailored for arbitrarydimensional quantum systems and arbitrary quantum hardware restrictions. We demonstrated the results through gatemodel quantum computer architectures; however, due to the flexibility of the scheme, arbitrary implementations and input constraints can be integrated into the quantum circuit minimization. The objective function that is the subject of the maximization in the method can also be selected arbitrarily. This allows a flexible implementation to solve any computational problem for experimental quantum computers with arbitrary hardware restrictions and development constraints.
Notes
Acknowledgements
Open access funding provided by Budapest University of Technology and Economics (BME). This work was partially supported by the European Research Council through the Advanced Fellow Grant, in part by the Royal Society’s Wolfson Research Merit Award, in part by the Engineering and Physical Sciences Research Council under Grant EP/L018659/1, by the Hungarian Scientific Research Fund—OTKA K112125, and in part by the Engineering and Physical Sciences Research Council under Grant EP/L018659/1.
Author Contributions
LGY designed the protocol and wrote the manuscript. LGY and SI analyzed the results. All authors reviewed the manuscript.
Compliance with ethical standards
Conflict of interest
We have no competing financial interests.
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