Towards quantum reversible ternary coded decimal adder

  • Majid HaghparastEmail author
  • Robert Wille
  • Asma Taheri Monfared


Quantum ternary logic is a promising emerging technology for the future quantum computing. Ternary reversible logic circuit design has potential advantages over the binary ones like its logarithmic reduction in the number of qudits. In reversible logic all computations are done in an invertible fashion. In this paper, we propose a new quantum reversible ternary half adder with quantum cost of only 7 and a new quantum ternary full adder with a quantum cost of only 14. We termed it QTFA. Then we propose 3-qutrit parallel adders. Two different structures are suggested: with and without input carry. Next, we propose quantum ternary coded decimal (TCD) detector circuits. Two different approaches are investigated: based on invalid numbers and based on valid numbers. Finally, we propose the quantum realization of TCD adder circuits. Also here, two approaches are discussed. Overall, the proposed reversible ternary full adder is the best between its counterparts comparing the figures of merits. The proposed 3-qutrit parallel adders are compared with the existing designs and the improvements are reported. On the other hand, this paper suggested the quantum reversible TCD adder designs for the first time. All the proposed designs are realized using macro-level ternary Toffoli gates which are built on the top of the ion-trap realizable ternary 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.


Quantum computing Reversible logic Ternary logic Ternary coded decimal adder Ion-trap Ternary reversible full adder QTFA 


  1. 1.
    Landauer, R.: Irreversibility and heat generation in the computation process. IBM J. Res. Dev. 5, 183–191 (1961)CrossRefzbMATHGoogle Scholar
  2. 2.
    Bennett, C.: Logical reversibility of computations. IBM J. Res. Dev. 17, 525–532 (1973)CrossRefzbMATHMathSciNetGoogle Scholar
  3. 3.
    Gershenfeld, N.: Signal entropy and the thermodynamics of computation. IBM Syst. J. 35(3.4), 577–586 (1996)CrossRefGoogle Scholar
  4. 4.
    Zhirnov, V.V., Cavin, R.K., Hutchby, J.A., Bourianoff, G.I.: Limits to binary logic switch scaling–a Gedanken model. Proc. IEEE 91(11), 1934–1939 (2003)CrossRefGoogle Scholar
  5. 5.
    Nielsen, M., Chuang, I.: Quantum Computation and Quantum Information. Cambridge University Press, Cambridge (2000)zbMATHGoogle Scholar
  6. 6.
    Wille, R., et al.: SyReC: a hardware description language for the specification and synthesis of reversible circuits. Integr. VLSI J. 53, 39–53 (2016)CrossRefGoogle Scholar
  7. 7.
    Anderlini, M., Lee, P.J., Brown, B.L., Sebby-Strabley, J., Phillips, W.D., Porto, J.V.: Controlled exchange interaction between pairs of neutral atoms in an optical lattice (2007). arXiv preprint arXiv:0708.2073
  8. 8.
    Plantenberg, J.H., De Groot, P.C., Harmans, C.J.P.M., Mooij, J.E.: Demonstration of controlled-NOT quantum gates on a pair of superconducting quantum bits. Nature 447(7146), 836 (2007)ADSCrossRefGoogle Scholar
  9. 9.
    Fedorov, A., Steffen, L., Baur, M., da Silva, M.P., Wallraff, A.: Implementation of a Toffoli gate with superconducting circuits. arXiv preprint (2011). arXiv:1108.3966
  10. 10.
    White, A.G., Gilchrist, A., Pryde, G.J., O’Brien, J.L., Bremner, M.J., Langford, N.K.: Measuring two-qubit gates. JOSA B 24(2), 172–183 (2007)Google Scholar
  11. 11.
    Gao, W.B., Xu, P., Yao, X.C., Gühne, O., Cabello, A., Lu, C.Y., Pan, J.W.: Experimental realization of a controlled-NOT gate with four-photon six-qubit cluster states. Phys. Rev. Lett. 104(2), 020501 (2010)ADSCrossRefGoogle Scholar
  12. 12.
    Khan, M.H., Perkowski, M.A.: Quantum ternary parallel adder/subtractor with partially-look-ahead carry. J. Syst. Archit. 53(7), 453 (2007)CrossRefGoogle Scholar
  13. 13.
    Muthukrishnan, A., Stroud Jr., C.R.: Multivalued logic gates for quantum computation. Phys. Rev. A 62(5), 052309-1–8 (2000)Google Scholar
  14. 14.
    Klimov, A.B., Guzman, R., Retamal, J.C., Saavedra, C.: Qutrit quantum computer with trapped ions. Phys. Rev. A 67(6), 062313-1–7 (2003)Google Scholar
  15. 15.
    McHugh, D., Twamley, J.: Trapped-ion qutrit spin molecule quantum computer. New J. Phys. 7(1), 174-1–9 (2005)Google Scholar
  16. 16.
    Yang, G., Song, X., Perkowski, M., Wu, J.: Realizing ternary quantum switching networks without ancilla bits. J. Phys. A: Math. Gen. 38, 1–10 (2005)CrossRefzbMATHMathSciNetGoogle Scholar
  17. 17.
    Miller, D.M., Thornton, M.A.: Multiple valued logic: concepts and representations. Synth. Lect. Dig. Circuits Syst. 2(1), 1–127 (2007)CrossRefGoogle Scholar
  18. 18.
    De Vos, A., van Rentergem, Y.: Multiple-valued reversible logic circuits. J. Mult.-Valued Log. Soft Comput. 15(4–5), 489–505 (2009)zbMATHGoogle Scholar
  19. 19.
    Houshmand, P.: Haghparast, Majid: Design of a novel quantum reversible ternary up-counter. Int. J. Quantum Inf. 13(05), 1550038 (2015)CrossRefzbMATHGoogle Scholar
  20. 20.
    Monfared, A.T., Haghparast, M.: Novel design of quantum/reversible ternary comparator circuits. J. Comput. Theor. Nanosci. 12(12), 5670–5673 (2015)CrossRefGoogle Scholar
  21. 21.
    Monfared, A.T.: Design of new quantum/reversible ternary subtractor circuits. J. Circuits Syst. Comput. 25(02), 1650014 (2016)CrossRefGoogle Scholar
  22. 22.
    Monfared, A.T., Haghparast, M.: Design of novel quantum/reversible ternary adder circuits. Int. J. Electron. Lett. 5(2), 149–157 (2017)CrossRefGoogle Scholar
  23. 23.
    Haghparast, M.: Monfared, Asma Taheri: Novel quaternary quantum decoder, multiplexer and demultiplexer circuits. Int. J. Theor. Phys. 56(5), 1694–1707 (2017)CrossRefzbMATHGoogle Scholar
  24. 24.
    Haghparast, M, Dousttalab, N: On design of new reversible quaternary flip-flops. Int. J. Quantum Inf. 15(4), 1750024-1–1750024-11 (2017)Google Scholar
  25. 25.
    Chau, H.F.: Correcting quantum errors in higher spin systems. Phys. Rev. A 55(2), R839 (1997)ADSCrossRefGoogle Scholar
  26. 26.
    Khan, M.H.A.: GFSOP-based ternary quantum logic synthesis. In: Optics and Photonics for Information Processing IV, Proceedings of SPIE, vol. 7797 (2010)Google Scholar
  27. 27.
    Zadeh, R.P., Haghparast, M.: A new reversible/quantum ternary comparator. Aust. J. Basic Appl. Sci. 5(12), 2348–2355 (2011)Google Scholar
  28. 28.
    Raja, M.K., Koppala, N.: Modeling and implementation of reliable ternary arithmetic and logic unit design using Vhdl. Int. J. Eng. Res. Appl. 4(6), 259–264 (2014)Google Scholar
  29. 29.
    Nisbet-Jones, P.B., Dilley, J., Holleczek, A., Barter, O., Kuhn, A.: Photonic qubits, qutrits and ququads accurately prepared and delivered on demand. New J. Phys. 15(5), 053007 (2013)ADSCrossRefGoogle Scholar
  30. 30.
    Bocharov, A., Roetteler, M., Svore, K.M.: Factoring with qutrits: Shor’s algorithm on ternary and metaplectic quantum architectures. Phys. Rev. A 96(1), 012306 (2017)ADSCrossRefGoogle Scholar
  31. 31.
    Thew, R. T., Acin, A., Zbinden, H., Gisin, N.: Quantum Information and Computation, in print. arXiv preprint arXiv:quant-ph/0512125
  32. 32.
    Langford, N.K., Dalton, R.B., Harvey, M.D., O’Brien, J.L., Pryde, G.J., Gilchrist, A., White, A.G.: Measuring entangled qutrits and their use for quantum bit commitment. Phys. Rev. Lett. 93(5), 053601 (2004)ADSCrossRefGoogle Scholar
  33. 33.
    Molina-Terriza, G., Vaziri, A., Řeháček, J., Hradil, Z., Zeilinger, A.: Triggered qutrits for quantum communication protocols. Phys. Rev. Lett. 92(16), 167903 (2004)ADSCrossRefGoogle Scholar
  34. 34.
    Howell, J.C., Lamas-Linares, A., Bouwmeester, D.: Experimental violation of a spin-1 Bell inequality using maximally entangled four-photon states. Phys. Rev. Lett. 88(3), 030401 (2002)ADSCrossRefGoogle Scholar
  35. 35.
    Ralph, T.C., Resch, K.J., Gilchrist, A.: Efficient Toffoli gates using qudits. Phys. Rev. A 75(2), 022313 (2007)ADSCrossRefGoogle Scholar
  36. 36.
    Bartlett, S.D., de Guise, H., Sanders, B.C.: Quantum encodings in spin systems and harmonic oscillators. Phys. Rev. A 65(5), 052316 (2002)ADSCrossRefGoogle Scholar
  37. 37.
    Lanyon, B.P., Barbieri, M., Almeida, M.P., Jennewein, T., Ralph, T.C., Resch, K.J., White, A.G.: Simplifying quantum logic using higher-dimensional Hilbert spaces. Nat. Phys. 5(2), 134 (2009)CrossRefGoogle Scholar
  38. 38.
    Collins, D., Gisin, N., Linden, N., Massar, S., Popescu, S.: Bell inequalities for arbitrarily high-dimensional systems. Phys. Rev. Lett. 88(4), 040404 (2002)ADSCrossRefzbMATHMathSciNetGoogle Scholar
  39. 39.
    Kaszlikowski, D., Kwek, L.C., Chen, J.L., Żukowski, M., Oh, C.H.: Clauser-Horne inequality for three-state systems. Phys. Rev. A 65(3), 032118 (2002)ADSCrossRefGoogle Scholar
  40. 40.
    Cohen, I., Retzker, A.: Proposal for verification of the haldane phase using trapped ions. Phys. Rev. Lett. 112(4), 040503 (2014)ADSCrossRefGoogle Scholar
  41. 41.
    Bruß, D., Macchiavello, C.: Optimal eavesdropping in cryptography with three-dimensional quantum states. Phys. Rev. Lett. 88(12), 127901 (2002)ADSCrossRefGoogle Scholar
  42. 42.
    Cerf, N.J., Bourennane, M., Karlsson, A., Gisin, N.: Security of quantum key distribution using d-level systems. Phys. Rev. Lett. 88(12), 127902 (2002)ADSCrossRefGoogle Scholar
  43. 43.
    Mohammadi, M., Eshghi, M., Haghparast, M.: On design of multiple-valued sequential reversible circuits for nanotechnology based systems. In: Proceedings of the IEEE Region 10 Conference (TENCON) (2008)Google Scholar
  44. 44.
    Khan, M.H.A.: Design of ternary reversible sequential circuits. In: 2014 International Conference on Electrical and Computer Engineering (ICECE), IEEE (2014)Google Scholar
  45. 45.
    Deibuk, V.G., Biloshytskyi, A.V.: Design of a ternary reversible/quantum adder using genetic algorithm. Int. J. Inf. Technol. Comput. Sci. (IJITCS) 7(9), 38 (2015)Google Scholar
  46. 46.
    Lisa, N.J., Babu, H.M.H.: Design of a compact ternary parallel adder/subtractor circuit in quantum computing. In: 2015 IEEE International Symposium on Multiple-Valued Logic (ISMVL), pp. 36–41. May 2015Google Scholar
  47. 47.
    Khan, M.H., Perkowski, M.: Quantum realization of ternary encoder and decoder. In: Proceedings of the 7th International Symposium on Representations and Methodology of Future Computing Technologies (RM2005), Tokyo, Sept 2005Google Scholar
  48. 48.
    Khan, M.H.: Design of reversible/quantum ternary multiplexer and demultiplexer. Eng. Lett. 13(2), 65–69 (2006)Google Scholar
  49. 49.
    Khan, M.H.: Design of reversible/quantum ternary comparator circuits. Eng. Lett. 16(2), 178–184 (2008)Google Scholar
  50. 50.
    Deibuk, V., Biloshytskyi, A.: Genetic synthesis of new reversible/quantum ternary comparator. Adv. Electr. Comput. Eng. 15(3), 147–152 (2015)CrossRefGoogle Scholar
  51. 51.
    Khan, M.H.A., Perkowski, M.A., Kerntopf, P.: Multi-output Galois field sum of products synthesis with new quantum cascades. In: 33rd International Symposium on Multiple-Valued Logic, 2003. Proceedings. IEEE (2003)Google Scholar
  52. 52.
    De Vos, A., Birger, R., Storme, L.: Generating the group of reversible logic gates. J. Phys. A: Math. Gen. 35(33), 7063 (2002)ADSCrossRefzbMATHMathSciNetGoogle Scholar
  53. 53.
    Miller, D.M., Dueck, G.W., Maslov, D.: A synthesis method for MVL reversible logic [multiple value logic]. In: Proceedings. 34th International Symposium on Multiple-Valued Logic, 2004. pp. 74–80. May 2004Google Scholar
  54. 54.
    Miller, D.M., Maslov, D., Dueck, G.W.: Synthesis of quantum multiple-valued circuits. J. Mult.-Valued Log. Soft Comput. 12, 5–6 (2006)zbMATHMathSciNetGoogle Scholar
  55. 55.
    Dubrova, E.V., Muzio, J.C.: Generalized Reed-Muller canonical form for a multiple-valued algebra. Int. J. Mult. Valued Log. 1, 65–84 (1996)zbMATHGoogle Scholar
  56. 56.
    Mohammadi, M., Niknafs, A., Eshghi, M.: Controlled gates for multi-level quantum computation. Quantum Inf. Process. 10(2), 241–256 (2011)CrossRefzbMATHMathSciNetGoogle Scholar
  57. 57.
    Mohammadi, M.: Radix-independent, efficient arrays for multi-level n-qudit quantum and reversible computation. Quantum Inf. Process. 14(8), 2819–2832 (2015)ADSCrossRefzbMATHMathSciNetGoogle Scholar
  58. 58.
    Barenco, A., et al.: Elementary gates for quantum computation. Phys. Rev. A 52(5), 3457 (1995)ADSCrossRefGoogle Scholar
  59. 59.
    Mounika, J., Ramanujam, K., Jahangir, M.Z.: CMOS based design and simulation of ternary full adder and Ternary Coded Decimal (TCD) adder circuit. In: 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), pp. 1–5. March 2016Google Scholar
  60. 60.
    Khan, M., Rice, J.E.: Synthesis of reversible logic functions using ternary Max-Min algebra. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1674–1677. May 2016Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Department of Computer Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey BranchIslamic Azad UniversityTehranIran
  2. 2.Institute for Integrated CircuitsJohannes Kepler UniversityLinzAustria
  3. 3.Department of Computer, Abadan BranchIslamic Azad UniversityAbadanIran

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