Quantum Information Processing

, Volume 10, Issue 3, pp 355–377 | Cite as

Synthesis of quantum circuits for linear nearest neighbor architectures

  • Mehdi SaeediEmail author
  • Robert Wille
  • Rolf Drechsler


While a couple of impressive quantum technologies have been proposed, they have several intrinsic limitations which must be considered by circuit designers to produce realizable circuits. Limited interaction distance between gate qubits is one of the most common limitations. In this paper, we suggest extensions of the existing synthesis flow aimed to realize circuits for quantum architectures with linear nearest neighbor interaction. To this end, a template matching optimization, an exact synthesis approach, and two reordering strategies are introduced. The proposed methods are combined as an integrated synthesis flow. Experiments show that by using the suggested flow, quantum cost can be improved by more than 50% on average.


Quantum circuits Logic synthesis Nearest neighbor architectures Template matching 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Wille, R., Saeedi, M., Drechsler, R.: Synthesis of reversible functions beyond gate count and quantum cost. In: International Workshop on Logic Synthesis, pp. 43–49 (2009)Google Scholar
  2. 2.
    Nielsen M., Chuang I.: Quantum Computation and Quantum Information. Cambridge University Press, Cambridge (2000)zbMATHGoogle Scholar
  3. 3.
    Mosca, M.: Quantum algorithms. Springer Encyclopedia of Complexity and Systems Science (to appear) (2008)Google Scholar
  4. 4.
    Meter R.V., Oskin M.: Architectural implications of quantum computing technologies. J. Emerg. Technol. Comput. Syst. 2(1), 31–63 (2006)CrossRefGoogle Scholar
  5. 5.
    Ross M., Oskin M.: Quantum computing. Commun. ACM 51(7), 12–13 (2008)CrossRefGoogle Scholar
  6. 6.
    Knill E., Laflamme R., Milburn G.J.: A scheme for efficient quantum computation with linear optics. Nature 409, 46–52 (2001)PubMedCrossRefADSGoogle Scholar
  7. 7.
    Fowler A.G., Devitt S.J., Hollenberg L.C.L.: Implementation of shor’s algorithm on a linear nearest neighbour qubit array. Quantum Information and Computation 4, 237–245 (2004)zbMATHMathSciNetGoogle Scholar
  8. 8.
    Häffner H., Hänsel W., Roos C.F., Benhelm J., Chek al kar D., Chwalla M., Körber T., Rapol U.D., Riebe M., Schmidt P.O., Becher C., Gühne O., Dür W., Blatt R.: Scalable multiparticle entanglement of trapped ions. Nature 438, 643–646 (2005)PubMedCrossRefADSGoogle Scholar
  9. 9.
    Laforest M., Simon D., Boileau J.-C., Baugh J., Ditty M., Laflamme R.: Using error correction to determine the noise model. Phys. Rev. A 75, 133–137 (2007)CrossRefGoogle Scholar
  10. 10.
    Kane B.: A silicon-based nuclear spin quantum computer. Nature 393, 133–137 (1998)CrossRefADSGoogle Scholar
  11. 11.
    Maslov, D.: Linear depth stabilizer and quantum fourier transformation circuits with no auxiliary qubits in finite neighbor quantum architectures. Phys. Rev. A 76 (2007)Google Scholar
  12. 12.
    Takahashi Y., Kunihiro N., Ohta K.: The quantum fourier transform on a linear nearest neighbor architecture. Quantum Information and Computation 7, 383–391 (2007)zbMATHMathSciNetGoogle Scholar
  13. 13.
    Kutin, S.A.: Shor’s algorithm on a nearest-neighbor machine. Asian Conference on Quantum Information Science (2007)Google Scholar
  14. 14.
    Choi, B.-S., Van Meter, R.: Effects of Interaction Distance on Quantum Addition Circuits. ArXiv e-prints (September 2008)Google Scholar
  15. 15.
    Fowler A.G., Hill C.D., Hollenberg L.C.L.: Quantum error correction on linear nearest neighbor qubit arrays. Phys. Rev. A 69, 042314.1–042314.4 (2004)CrossRefADSGoogle Scholar
  16. 16.
    Möttönen M., Vartiainen J.J.: Decompositions of General Quantum Gates. Chapter 7 in Trends in Quantum Computing Research. NOVA Publishers, New York (2006)Google Scholar
  17. 17.
    Shende V.V., Bullock S.S., Markov I.L.: Synthesis of quantum-logic circuits. IEEE Trans. on CAD 25(6), 1000–1010 (2006)Google Scholar
  18. 18.
    Cheung, D., Maslov, D., Severini, S.: Translation techniques between quantum circuit architectures. Workshop on Quantum Information Processing (December 2007)Google Scholar
  19. 19.
    Chakrabarti A., Sur-Kolay S.: Nearest neighbour based synthesis of quantum boolean circuits. Eng. Lett. 15, 356–361 (2007)Google Scholar
  20. 20.
    Khan M.H.A.: Cost reduction in nearest neighbour based synthesis of quantum boolean circuits. Eng. Lett. 16, 1–5 (2008)ADSGoogle Scholar
  21. 21.
    Hirata, Y., Nakanishi, M., Yamashita, S., Nakashima, Y.: An efficient method to convert arbitrary quantum circuits to ones on a linear nearest neighbor architecture. In: International Conference on Quantum, Nano and Micro Technologies, pp. 26–33 (2009)Google Scholar
  22. 22.
    Lee, S., Lee, S.J., Kim, T., Lee, J.S., Biamonte, J., Perkowski, M.: The cost of quantum gate primitives. J. Multiple Value Logic Soft Comput. 12(5–6) (2006)Google Scholar
  23. 23.
    Barenco A., Bennett C., Cleve R., DiVincenzo D., Margolus N., Shor P., Sleator T., Smolin J., Weinfurter H.: Elementary gates for quantum computation. APS Phys. Rev. A 52, 3457–3467 (1995)ADSGoogle Scholar
  24. 24.
    Maslov D., Dueck G.W., Miller D.M., Negrevergne C.: Quantum circuit simplification and level compaction. IEEE Trans. on CAD 27(3), 436–444 (2008)Google Scholar
  25. 25.
    Hung W.N.N., Song X., Yang G., Yang J., Perkowski M.: Optimal synthesis of multiple output boolean functions using a set of quantum gates by symbolic reachability analysis. IEEE Trans. on CAD 25(9), 1652–1663 (2006)Google Scholar
  26. 26.
    Große, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact synthesis of elementary quantum gate circuits for reversible functions with don’t cares. International Symposium on Multiple Valued Logic, pp. 214–219 (2008)Google Scholar
  27. 27.
    Maslov D., Dueck G.W., Michael Miller D.: Toffoli network synthesis with templates. IEEE Trans. on CAD 24(6), 807–817 (2005)Google Scholar
  28. 28.
    Maslov D., Dueck G.W., Miller D.M.: Techniques for the synthesis of reversible toffoli networks. ACM Trans. Des. Autom. Electron. Syst. 12(4), 42 (2007)CrossRefGoogle Scholar
  29. 29.
    Saeedi, M., Sedighi, M., Saheb Zamani, M.: A novel synthesis algorithm for reversible circuits. IEEE/ACM International Conference on Computer-aided design, pp. 65–68 (2007)Google Scholar
  30. 30.
    Gupta P., Agrawal A., Jha N.K.: An algorithm for synthesis of reversible logic circuits. IEEE Trans. on CAD 25(11), 2317–2330 (2006)Google Scholar
  31. 31.
    Große D., Wille R., Dueck G.W., Drechsler R.: Exact multiple control toffoli network synthesis with SAT techniques. IEEE Trans. on CAD 28(5), 703–715 (2009)Google Scholar
  32. 32.
    Wille, R., Drechsler, R.: BDD-based synthesis of reversible logic for large functions. In: DAC ’09: Proceedings of the 46th annual Design Automation Conference, pp. 270–275 (2009)Google Scholar
  33. 33.
    Saeedi M., Sedighi M., Zamani M. Saheb: A library-based synthesis methodology for reversible logic. Elsevier Microelectron. J. 41(4), 185–194 (2010)Google Scholar
  34. 34.
    Saeedi, M., Zamani M., Saheb, Sedighi, M., Sasanian, Z.: Synthesis of reversible circuit using cycle-based approach. ACM J. Emerg. Technol. Comput. Syst. (2010)
  35. 35.
    Miller, D. Michael, Maslov, Dmitri, Dueck, Gerhard W.: A transformation based algorithm for reversible logic synthesis. In: DAC ’03: Proceedings of the 40th annual Design Automation Conference, pp. 318–323. New York, NY: ACM (2003)Google Scholar
  36. 36.
    Chakrabarti, A., Sur-Kolay, S.: Rules for synthesizing quantum boolean circuits using minimized nearest-neighbour templates. In: International Conference on Advanced Computing and Communications, pp. 183–189 (2007)Google Scholar
  37. 37.
    Barenco A., Ekert A., Suominen K.-A., Törmä P.: Approximate quantum fourier transform and decoherence. Phys. Rev. A 54(1), 139–146 (1996)PubMedCrossRefADSMathSciNetGoogle Scholar
  38. 38.
    Wille, R., Große, D., Dueck, G.W., Drechsler, R.: Reversible logic synthesis with output permutation. In: VLSID ’09: Proceedings of the 2009 22nd International Conference on VLSI Design, pp. 189–194, Washington, DC, USA: IEEE Computer Society (2009)Google Scholar
  39. 39.
    Wille, R., Große, D., Teuber, L., Dueck, G.W., Drechsler, R.: Revlib: An online resource for reversible functions and reversible circuits. International Symposium on Multiple Valued Logic, pp. 220–225 (May 2008)Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  1. 1.Computer Engineering DepartmentAmirkabir University of TechnologyTehranIran
  2. 2.Institute of Computer ScienceUniversity of BremenBremenGermany

Personalised recommendations