Natural Computing

, Volume 12, Issue 3, pp 353–368 | Cite as

Explicit routing schemes for implementation of cellular automata on processor arrays

Article

Abstract

Massively parallel processor array (MPPA) architectures are becoming widely available computing platforms. Because of formal similarities, they are good candidates for implementing cellular automata (CA). An essential difference still remains regarding the freedom in communications. In MPPA there is a fixed on-chip network interconnection topology but every CA has its own definition of neighbourhood. While a cell in a CA can be considered as directly connected to its neighbours, these connections correspond to paths in the network of the MPPA. The communications need to be routed and scheduled to reach their proper destination. In previous work we introduced a formal data-flow process network model named KRG (for K-periodically Routed Graph). Its main feature is to allow regular switching directives. In the present paper we will use it to represent the proper local sequences of routing directives that will efficiently propagate values from cells to cells so as to implement the required CA neighbourhood. We present the neighbourhood broadcasting algorithm that computes these routing directives. One should note here that the problem is made more complex as data traffic between distinct source and target cells must be merged, while multicast may save a tremendous amount of communications when values are required in multiple locations. We demonstrate the expressive power of our formalism on the case of a 2D CA where the neighbourhood consists of all cells at Moore distance at most n. Further potential applications of our framework are hinted.

Keywords

Adequation algorithm architecture Cellular automata Data-flow process network Massively parallel processor array Network-on-chip Routing 

References

  1. Accellera (2007) System C. http://www.accellera.org/downloads/standards/systemc. Accessed 1 Oct 2012
  2. Benveniste A, Caspi P, Edwards SA, Halbwachs N, Guernic PL, de Simone R (2003) The synchronous languages 12 years later. Proc IEEE 91(1):64–83 doi:10.1109/JPROC.2002.805826 CrossRefGoogle Scholar
  3. Bilsen G, Engels M, Lauwereins R, Peperstraete J (1995) Cyclo-static data flow. In: Acoustics, Speech, and Signal Processing, 1995. ICASSP-95., 1995 International Conference on, vol 5, pp 3255 –3258, doi:10.1109/ICASSP.1995.479579
  4. Boucaron J, Coadou A, de Simone R (2010) Synthesis of embedded software: frameworks and methodologies for correctness by construction software design, Shukla, Sandeep Kumar and Talpin, Jean-Pierre, Springer, Heidelberg, chap 2, pp 41–78Google Scholar
  5. Bouré O, Fatès N, Chevrier V (2011) Robustness of cellular automata in the light of asynchronous information transmission. In: Proceedings of the 10th international conference on Unconventional computation, Springer, Berlin, UC’11, pp 52–63. URL http://dl.acm.org/citation.cfm?id=2022023.2022036
  6. Chaudhuri PP, Chowdhury DR, Nandi S, Chattopadhyay S (1997) Additive Cellular Automata. Wiley-IEEE Computer Society Press. Los Alamitos, CaliforniaGoogle Scholar
  7. Coadou A (2010) Réseaux de processus flots de données avec routage pour la modélisation de systèmes embarqués. PhD thesis, University of Nice Sophia AntipolisGoogle Scholar
  8. Cohen A, Duranton M, Eisenbeis C, Pagetti C, Plateau F, Pouzet M (2006) N-synchronous kahn networks. In: POPL 2006 Proceedings, pp. 180–193Google Scholar
  9. Commoner F, Holt AW, Even S, Pnueli A (1971) Marked directed graph. J Comput Syst Sci 5:511–523MathSciNetMATHCrossRefGoogle Scholar
  10. Datta K, Murphy M, Volkov V, Williams S, Carter J, Oliker L, Patterson D, Shalf J, Yelick K (2008) Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures. In: Proceedings of the 2008 ACM/IEEE conference on Supercomputing, IEEE Press, Piscataway, NJ, USA, SC ’08, pp 4:1–4:12, URL http://dl.acm.org/citation.cfm?id=1413370.1413375
  11. Datta K, Williams S, Volkov V, Carter J, Oliker L, Shalf J, Yelick K (2009) Auto-tuning the 27-point stencil for multicore. In: Proc. iWAPT2009: The Fourth International Workshop on Automatic Performance TuningGoogle Scholar
  12. Davare A, Densmore D, Meyerowitz T, Pinto A, Sangiovanni-Vincentelli A, Yang G, Zeng H, Zhu Q (2007) A next-generation design framework for platform-based design. In: DVCon 2007. URL http://chess.eecs.berkeley.edu/pubs/228.html
  13. Dennunzio A (2012) From one-dimensional to two-dimensional cellular automata. Fundamenta Informaticae 115(1):87–105MathSciNetMATHGoogle Scholar
  14. Eker J, Janneck J, Lee E, Liu J, Liu X, Ludvig J, Neuendorffer S, Sachs S, Xiong Y (2003) Taming heterogeneity—the ptolemy approach. Proc IEEE 91(1):127–144 doi:10.1109/JPROC.2002.805829 CrossRefGoogle Scholar
  15. Ferrari A, Sangiovanni-Vincentelli A (1999) System design: traditional concepts and new paradigms. In: Computer Design, 1999. (ICCD ’99) International Conference on, pp. 2–12, doi:10.1109/ICCD.1999.808256
  16. Gardner M (1970) The fantastic combinations of john conway’s new solitaire game “life". Sci Am 223:120–123CrossRefGoogle Scholar
  17. Glitia C, DeAntoni J, Mallet F, Millo JV, Boulet P, Gamatié A (2012) Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte. Des Autom Embed Syst 16:137–169 doi:10.1007/s10617-012-9093-y CrossRefGoogle Scholar
  18. Grandpierre T, Lavarenne C, Sorel Y (1999) Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors. In: Proceedings of 7th International Workshop on Hardware/Software Co-Design, CODES’99, Rome, ItalyGoogle Scholar
  19. Halbach M, Hoffmann R (2004) Implementing cellular automata in fpga logic. In: Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International, pp. 258 doi:10.1109/IPDPS.2004.1303324
  20. Herrera F, Villar E (2011) A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation. Specification and Design Languages (FDL), 2011 Forum on. pp 1–8Google Scholar
  21. Jantsch A (2008) Models of computation for distributed embedded systems. In: Zurawski R (ed) Networked embedded systems, chap 3, CRC Press/Taylor & Francis, Boca Raton/LondonGoogle Scholar
  22. Kalray (2012) Mppa manycore. http://www.kalray.eu/products/mppa-manycore. Accessed 1 Oct 2012
  23. Kari J (2005) Theory of cellular automata: A survey. Theoret Comput Sci 334(1-3):3–33 doi:10.1016/j.tcs.2004.11.021 MathSciNetMATHCrossRefGoogle Scholar
  24. Kobori T, Maruyama T, Hoshino T (2001) A cellular automata system with fpga. In: Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, IEEE Computer Society, Washington, DC, USA, FCCM ’01, pp 120–129, doi:10.1109/FCCM.2001.2
  25. Marouf M, Sorel Y (2011) Scheduling non-preemptive hard real-time tasks with strict periods. In: Proceedings of 16th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA’11, Toulouse, France, pp 1–8Google Scholar
  26. Melpignano D, Benini L, Flamand E, Jego B, Lepley T, Haugou G, Clermidy F, Dutoit D (2012) Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications. In: Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE. pp1137–1142Google Scholar
  27. de Micheli G, Benini L (2006) Networks on chips. Morgan Kauffmann, Elsevier, AmsterdamGoogle Scholar
  28. Millo JV, de Simone R (2012a) Periodic scheduling of MGs using balanced binary words. Theoret Comput Sci 458:113-130 doi:10.1016/j.tcs.2012.08.012 MathSciNetMATHCrossRefGoogle Scholar
  29. Millo JV, de Simone R (2012b) Refining cellular automata with routing constraints. In: Formenti E (ed) Automata & JAC (Exploratory track), vol 2. I3S UMR 7172 - UNS CNRS, Sophia-Antipolis, France, p 15Google Scholar
  30. Parks T (1995) Bounded scheduling of process networks. PhD thesis, EECS, Department, University of California, Berkeley CA 94720, technical Report UCB/ERL-95-105Google Scholar
  31. Rybacki S, Himmelspach J, Uhrmacher AM (2009) Experiments with single core, multi-core, and gpu based computation of cellular automata. In: Proceedings of the 2009 First International Conference on Advances in System Simulation, IEEE Computer Society, Washington, DC, USA, SIMUL ’09, pp 62–67, doi:10.1109/SIMUL.2009.36
  32. Sangiovanni-Vincentelli AL, Passerone R (2012) Platform-based Design. Springer, New YorkGoogle Scholar
  33. Sriram S, Bhattacharyya SS (2009) Embedded multiprocessors, Scheduling and Synchronization. CRC Press, Boca RatonCrossRefGoogle Scholar
  34. Zaloudek L, Sekanina L, Simek V (2009) Gpu accelerators for evolvable cellular automata. In: Future computing, service computation, cognitive, adaptive, content, patterns, COMPUTATIONWORLD ’09. Computation World, pp. 533 –537, doi:10.1109/ComputationWorld.2009.49

Copyright information

© Springer Science+Business Media Dordrecht 2013

Authors and Affiliations

  1. 1.EPI AOSTE, INRIA Sophia-AntipolisSophia-AntipolisFrance

Personalised recommendations