Multidimensional Systems and Signal Processing

, Volume 25, Issue 4, pp 829–845 | Cite as

Algebraic integer architecture with minimum adder count for the 2-D Daubechies 4-tap filters banks

  • Shiva K. Madishetty
  • Arjuna Madanayake
  • Renato J. Cintra
  • Vassil S. Dimitrov
  • Dale H. Mugler
Brief Communication


A multiplierless architecture based on algebraic integer representation for computing the Daubechies 4-tap wavelet transform for 1-D/2-D signal processing is proposed. This architecture improves on previous designs in a sense that it minimizes the number of parallel 2-input adder circuits. The algorithm was achieved using numerical optimization based o exhaustive search over the algebraic integer representation. The proposed architecture furnishes exact computation up to the final reconstruction step, which is the operation that maps the exactly computed filtered results from algebraic integer representation to fixed-point. Compared to Madishetty et al. (IEEE Trans Circuits Syst I (Accepted, In Press), 2012a), this architecture shows a reduction of \(10\cdot n-3\) adder circuits, where \(n\) is the number of wavelet decomposition levels. Standard \(512\times 512\) images Mandrill, Lena, and Cameraman were submitted to digital realizations of both proposed algebraic integer based as well as fixed-point schemes, leading to quantifiable comparisons. The design is physically implemented for a 4-level 2-D decomposition using a Xilinx Virtex-6 vcx240t-1ff1156 FPGA device operating at up to a maximum clock frequency of 263.15 MHz. The FPGA implementation is tested using hardware co-simulation using an ML605 board with clock of 100 MHz. A 45 nm CMOS synthesis shows improved clock frequency of better than 500 MHz for a supply voltage of 1.1 V.


Algebraic integer encoding Daubechies wavelets Error-free algorithm Subband coding 



This work was supported by the University of Akron, Ohio, USA; the Conselho Nacional de Desenvolvimento Científico e Tecnológico (CPNq) and FACEPE, Brazil; and the Natural Science and Engineering Research Council (NSERC), Canada.


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Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Shiva K. Madishetty
    • 1
  • Arjuna Madanayake
    • 1
  • Renato J. Cintra
    • 2
  • Vassil S. Dimitrov
    • 3
  • Dale H. Mugler
    • 4
  1. 1.Department of Electrical and Computer EngineeringThe University of AkronAkronUSA
  2. 2.Signal Processing Group, Departamento de EstatísticaUniversidade Federal de PernambucoRecifeBrazil
  3. 3.Department of Electrical and Computer EngineeringUniversity of CalgaryCalgaryCanada
  4. 4.Department of Biomedical EngineeringThe University of AkronAkronUSA

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