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High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

  • Grande NagaJyothiEmail author
  • Sriadibhatla Sridevi
Article
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Abstract

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

Keywords

Distributed arithmetic Decision feedback equalizer Non-linear equalizer FIR Feed forward (FF) filter Feed back (FB) filter Linear equalizer Inter symbol interference (ISI) Quantizer 

Notes

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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Micro and Nano-electronicsVellore Institute of TechnologyVelloreIndia

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