Multimedia Tools and Applications

, Volume 76, Issue 4, pp 5905–5926 | Cite as

A high quality compiler tool for application-specific instruction-set processors with library and parallel supports

  • Benbin Chen
  • Chung-Ta King
  • Xiaochao Li
  • Donghui Guo
Article
  • 126 Downloads

Abstract

Developing a high quality compiler tool for application-specific instruction-set processors (ASIPs) including DSP for multimedia application is challenging. The specialization in ASIPs often calls for extensions at the high-level languages to allow the designers to exploit the specialized capabilities. This in turn requires the frontend of the compiler to handle the new syntax and carry the intentions of the designers across to the compiler backend implementations. The backend implementations also require extra efforts for optimized uses of the specialize features of ASIPs. Meanwhile, because of the diversity of the application, it is necessary to make full use of the compiler to complete supports and to make up some shortages of ASIP processors, the corresponding library functions are increased to support of certain operations, such as floating point arithmetic that may not be supported in ASIPs. With the development of the embedded parallelism, the advanced ASIP compilers need the support of parallelism for future application. This paper describes the High-performance C Compiler (HCC) and its specific implementation for an industrial ASIP and its family processors. HCC is a C language compiler extended and retargeted from GCC. A compiler extension framework is proposed processing programming syntax extensions of standard ANSI C for the ASIPs. With target-specific implementation, the adding optimized arithmetic functions library and chips definition file (CDF) as well as the header files for corresponding ASIPs, HCC compiler could be enhanced for the processing capabilities of target processors. Finally, this paper describes a new compiler static allocation and scheduling scheme for loop parallelization based on the OpenMP specification to improve the load imbalance. We have conducted analysis and extensive experiments to verify the correctness and effectiveness of the HCC compiler with the presented ideas. The results show that HCC compiler has a stable performance with excellent codes quality and it has been used in market.

Keywords

Application-specific instruction-set processor Multimedia application Retargeting compiler Library support OpenMP parallel specification 

References

  1. 1.
    Antani L, Ansari H, Parameswaran A (2007) Tricore Port for GCC-An Analysis. Department of Computer Science and Engineering, Indian Institute of Technology, Mumbai, IndianGoogle Scholar
  2. 2.
    Ayguade E, Copty N, Duran A, Hoeflinger J et al (2009) The design of OpenMP tasks. IEEE Trans Parallel Distrib Syst 20(3):404–418CrossRefGoogle Scholar
  3. 3.
    Chen BB, Guo DH (2014) A Static Scheduling Scheme of Multicore Compiler for Loop Load Imbalance in OpenMP. ASID 30–33Google Scholar
  4. 4.
    Cuadrado JS, Molina JG (2007) Building domain-specific languages for mod-el-driven development. IEEE Softw 24(5):48–55CrossRefGoogle Scholar
  5. 5.
    Desai NP (2009) A novel technique for orchestration of compiler optimization functions using branch and bound strategy. IACC 467–472Google Scholar
  6. 6.
    Feese S, Burscher MJ, Jonas K et al (2014) Sensing spatial and temporal coordination in teams using the smartphone. Human-centric Comput Inf Sci 4(1):1–18CrossRefGoogle Scholar
  7. 7.
    Guyer SZ, Lin C (2005) Broadway: A compiler for exploiting the domain-specific semantics of software libraries. J Proceedings of the IEEE 93(2):342–357Google Scholar
  8. 8.
    Hada R, Tanigawa K, Hironaka T (2008) A back-end compiler with fast compilation for VLIW based dynamic reconfigurable processor. WSEAS Trans Comput 7(9):1515–1524Google Scholar
  9. 9.
    Hsu PY, Liu YY (2014) Buffer design and assignment for structured ASIC. J Inf Sci Eng 30(1):107–124Google Scholar
  10. 10.
    Kim PS (2013) An architecture for home-oriented IPTV service platform on residential gateway. J Inf Process Syst 9(3):425–434CrossRefGoogle Scholar
  11. 11.
    Leupers R, Hohenauer M, Ceng J, Scharwaechter H, Meyr H, Ascheid G, Braun G (2005) Retargetable compilers and architecture exploration for embedded processors. IEE Comput Digit Tech 152(2):209–223CrossRefGoogle Scholar
  12. 12.
    Malkawi M (2013) The art of software systems development: Reliability, Availability, Maintainability, Performance (RAMP). Human-centric Comput Inf Sci 3(22):1–17Google Scholar
  13. 13.
    Mozgovoy M, Efimov R (2013) WordBricks: a virtual language lab inspired by Scratch environment and dependency grammars. Hum-centric Comput Inf Sci 3(1):1–9CrossRefGoogle Scholar
  14. 14.
    Nilsson (1998) Porting The GNU C Compiler to the CRIS architecture, Department of Information Technology. Lund Institute of Technology, SwedenGoogle Scholar
  15. 15.
    Oh JS, Park CU, Lee SB (2014) NFC-based mobile payment service adoption and diffusion. J Convergence 5(2):8–14Google Scholar
  16. 16.
    Ozturk O, Kandemir M, Chen G (2013) Compiler-directed energy reduction using dynamic voltage scaling and voltage islands for embedded systems. IEEE Trans Comput 62(2):268–278MathSciNetCrossRefGoogle Scholar
  17. 17.
    Panduranga HT, Naveen Kumar SK, Sharath Kumar HS (2013) Hardware software co-simulation of the multiple image encryption technique using the xilinx system generator. J Inf Process Syst 9(3):499–510CrossRefGoogle Scholar
  18. 18.
    Pei XH (2010) Porting GCC to Godson processor. University of Science and Technology of China, ChinaGoogle Scholar
  19. 19.
    Povazan I, Popovic M, Djukic M et al (2013) A retargetable C compiler for embedded systems. ECBS-EERC, Budapest 48–54Google Scholar
  20. 20.
    Ren K, Yan XL, Qin X, Sun LL (2008) Design and implementation of a novel ASIP compiler. J Zhejiang Univ 42(5):553–557Google Scholar
  21. 21.
    Seng JS, Tullsen DM (2003) The effect of compiler optimizations on Pentium 4 power consumption. INTERA 51–56Google Scholar
  22. 22.
    Tools of holtek semiconductor Inc. http://www.holtek.com.cn, 2014
  23. 23.
    Trienekens R (2009) Porting the GCC Compiler to a VLIW Vector Processor. Department of Electrical Engineering, Delft University of Technology, NetherlandsGoogle Scholar
  24. 24.
    Tzen TH, Ni LM (1993) Trapezoid self-scheduling: a practical scheduling scheme for parallel compilers. IEEE Trans Parallel Distrib Syst 4(1):87–98CrossRefGoogle Scholar
  25. 25.
    Wagner J, Leupers R (2001) C compiler design for a network processor. IEEE Trans Comput Aided Des Integr Circuits Syst 20(11):1302–1308CrossRefGoogle Scholar
  26. 26.
    Yang X, Peng G, Cai Z, Zeng K (2013) Occluded and low resolution face detection with hierarchical deformable model. J Convergence 4(1):11–14Google Scholar
  27. 27.
    Zaidi SMA, Jung J, Song B (2014) Prioritized multipath video forwarding in WSN. J Inf Process Syst 10(2):176–192CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Benbin Chen
    • 1
    • 2
  • Chung-Ta King
    • 3
  • Xiaochao Li
    • 1
  • Donghui Guo
    • 1
  1. 1.Department of Electronic EngineeringXiamen UniversityXiamenChina
  2. 2.School of Electrical Engineering and AutomationXiamen University of TechnologyFujianChina
  3. 3.Department of Computer ScienceNational Tsing Hua UniversityHsinchuTaiwan

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