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Journal of Low Temperature Physics

, Volume 167, Issue 5–6, pp 602–608 | Cite as

Development of Low Power Cryogenic Readout Integrated Circuits Using Fully-Depleted-Silicon-on-Insulator CMOS Technology for Far-Infrared Image Sensors

  • T. Wada
  • H. Nagata
  • H. Ikeda
  • Y. Arai
  • M. Ohno
  • K. Nagase
Article

Abstract

We are developing low power cryogenic readout integrated circuits (ROICs) for large format far-infrared image sensors using fully-depleted-silicon-on-insulator (FD-SOI) CMOS technology. We have evaluated the characteristics of MOS FETs fabricated by the FD-SOI CMOS technology and have found that both p-ch and n-ch FETs show good static performance below the liquid helium temperature, where n-ch FETs fabricated by conventional bulk-CMOS technology usually suffer from anomalous behaviors such as kink and hysteresis. We have also designed and fabricated an operational amplifier (OP-AMP) and have successfully demonstrated that the OP-AMP works at the liquid helium temperature with an open loop gain of 7000 and a power consumption of 1.3 μW. The noise is dominated by mainly 1/f and has a value of Open image in new window at 1 Hz.

Keywords

Low temperature Low power FD-SOI CMOS Readout IC Infrared astronomy 

Notes

Acknowledgements

This work was supported by KAKENHI (21760321, 23340053, 20244016).

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Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • T. Wada
    • 1
  • H. Nagata
    • 1
  • H. Ikeda
    • 1
  • Y. Arai
    • 2
  • M. Ohno
    • 3
  • K. Nagase
    • 1
    • 4
  1. 1.Institute of Space and Astronautical ScienceJapan Aerospace Exploration AgencySagamiharaJapan
  2. 2.High Energy Accelerator Research OrganizationTsukubaJapan
  3. 3.National Institute of Advanced Industrial Science and TechnologyTsukubaJapan
  4. 4.The Graduate University for Advanced StudiesSagamiharaJapan

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