Scientific complications and controversies noted in the field of CdS/CdTe thin film solar cells and the way forward for further development
Cadmium telluride-based solar cell is the most successfully commercialised thin film solar cell today. The laboratory-scale small devices have achieved ~ 22%, and commercial solar panels have reached ~ 18% conversion efficiencies. However, there are various technical complications and some notable scientific contradictions that appear in the scientific literature published since the early 1970s. This review paper discusses some of these major complications and controversies in order to focus future research on issues of material growth and characterisation, post-growth processing, device architectures and interpretation of the results. Although CdTe can be grown using more than 14 different growth techniques, successful commercialisation has been taken place using close-space sublimation and electrodeposition techniques only. The experimental results presented in this review are mainly based on electrodeposition. Historical trends of research and commercial successes have also been discussed compared to the timeline of novel breakthroughs in this field. Deeper understanding of these issues may lead to further increase in conversion efficiencies of this solar cell. Some novel ideas for further development of thin film solar cells are also discussed towards the end of this paper.
Acceleration of photovoltaic (PV) research started from the early 1970s with the first oil crisis and CdS/CdTe hetero-junction solar cell became one of the major thin film solar cells under intense research. Out of the two materials from the II–VI family, intrinsic CdS is inherently an n-type semiconductor and CdTe can exist in both n- and p-type electrical conduction intrinsically. However, since the CdS/CdTe hetero-junction showed good rectification properties, CdTe was assumed to be p-type in electrical conduction to form a p–n junction rectifying device with its n-CdS partner. Therefore, all the experimentally observed results were analysed and interpreted as a simple p–n hetero-junction [1, 2, 3, 4, 5, 6, 7, 8]. In parallel, theoretical calculations and simulations were also carried out for this solar cell assuming principles of p–n junction diodes [9, 10, 11, 12]. This is a classic example of following the same ideas in scientific research without critically testing the existing wisdom.
By the end of the 1980s, the conversion efficiency of this device gradually entered into double digits and Britt et al.  in 1993 reported 15.8% for a laboratory-scale device. The development progress became slow, and it took nearly another decade to increase the efficiency only by 0.7–16.5% by Wu et al. . In parallel to this scientific research, BP Solar initiated a scaling up process in the mid-1980s using electroplated CdTe and successfully manufactured 0.96-m2 solar panels with an efficiency of 10.6% . Although BP Solar was in the forefront of this technology, termination of this manufacturing work together with other solar energy activities around 2000 was a real setback for the development of CdS/CdTe solar cells. Although scientific research continued in academic and research institutes, the highest solar energy conversion efficiency was stagnated at 16.5% for another decade until ~ 2013.
While these solar cell development activities were taking place, electrical contacts to II–VI semiconductors were also progressed from mid-1980s [16, 17, 18]. Metal contacts to vacuum cleaved, air cleaved and chemically etched n-CdTe bulk materials showed a unique feature of Fermi level (FL) pinning at several experimentally observed defect levels . Furthermore, the chemically etched and Cd-rich CdTe surfaces produced excellent rectifying diodes when compared to Te-rich CdTe surfaces . Further work on polycrystalline CdTe thin films also showed similar behaviour and FL pinning at the same defect levels . As a result of this work, an alternative device architecture of n–n + Schottky Barrier (SB) was proposed in 2002  to describe the properties of TCO/CdS/CdTe/metal solar cells.
Around 2013, First Solar Company in the USA started to report rapid progress in the development of this device. The laboratory-scale efficiencies rapidly rose from reported 16.5 to ~ 22% in ~ 2017 [20, 21, 22] within a short period of 4 years. First Solar is now producing ~ 18% efficient solar panels becoming the largest thin film solar panel manufacturer in this field .
It is clear from the literature that the progress has been stagnated over a period of more than two decades before FirstSolar’s achievements in the field and there are several areas needing research attention. There are also some scientific disputes in the published works on this technologically important device. The main aim of this review paper is to identify these areas so that future research can be focussed to improve the understanding of materials and device issues. A better understanding of these issues will lead to further development of CdS/CdTe-based solar cell.
2 Noted contradictions and areas needing research attention
2.1 Materials growth and characterisation
2.1.1 Stoichiometry and electrical conductivity of CdTe
The literature shows that there are several different growth techniques used for the growth of CdS layers. Most popular techniques are the chemical bath deposition (CBD), close-space sublimation (CSS), sputtering and electrodeposition (ED). For the growth of CdTe layers, there are about 14 different growth techniques , but the commercially successful methods have been CSS and electrodeposition (ED). First Solar Company is successfully using modified CSS to produce high-efficiency devices, and the manufacturability of ED-CdTe has also been successfully proven by BP Solar . Because of the comprehensive research carried out by the authors of this article on electrodeposition of semiconductors, most of the examples given in this paper will be based on ED-CdTe thin films [25, 26], but the principles can also be applied to CdTe layers grown by other techniques.
Since Te is the easier element to electrodeposit, it has been identified that Te-precipitation takes place at nanoscale, and this has been reported before for electroplated CdTe thin films . Not only in ED-CdTe thin films, but also in CSS-CdTe thin films and melt-grown bulk CdTe, Te-precipitation has been observed [30, 31, 32]. This indicates that the Te-precipitation in CdTe is a natural feature and tends to produce p-type CdTe layers. As presented in later sections of this paper, n-type CdTe is more suitable for fabricating high-efficiency devices, and therefore, methods to prevent the formation of Te-precipitation should be established. Fernandez et al.  have shown that the incorporation of Ga removes Te-precipitates from CdTe. The positive effects of Ga incorporation on thin film CdTe solar cell efficiencies have been reported by Ojo et al. . Though this is not particularly a controversy, yet related research on preventing Te-precipitation in CdTe layers should be encouraged to develop CdS/CdTe solar cells further.
2.1.2 Intrinsic and extrinsic doping of CdTe
Intrinsic doping of CdTe is described using Fig. 1, in the above section by changing the Cd and Te compositions in ppm level. Another method to improve the electrical conduction in CdTe is extrinsic doping by adding selected external dopants into the material. For example, group-III (B, Al, Ga, In, …) and group-VII (halogens—F, Cl, Br, I) elements are suitable n-type dopants for CdTe . The positive results have been certainly observed with Ga and halogens (Cl, F and I). Similarly, group-I (Li, Na, K, Ag, Cu,…) and group-V (P, As, Sb, Bi,…) elements are suitable p-type dopants for CdTe . The literature reports ~ 1013–1015 cm−3 doping concentration for high-efficiency CdS/CdTe solar cells [13, 35, 36, 37]. Future research should be directed to increase these doping concentrations to ~ 1015–1016 cm−3 to improve CdS/CdTe solar cell performance, and extrinsic doping can play a vital role here. But unfortunately, the self-compensation mechanism due to native defects is high in CdTe, and therefore, the addition of these dopants does not always behave according to solid-state physics principles. Therefore, extrinsic doping of CdTe, if necessary, should be carried out with thorough understanding.
2.1.3 Chloride treatment and defects reduction
Cadmium chloride treatment or the activation step is a well-known processing step to increase the efficiency of CdS/CdTe thin film solar cells [38, 39, 40, 41]. Numerous publications are available on this treatment that includes the introduction of CdCl2 on to the CdTe surface and heat treatment in air at an optimised temperature for optimised time period. After a suitable chemical etching, an electrical contact is deposited to complete the glass/TCO/CdS/CdTe/electrical contact, solar cell. The research community agrees on changes such as grain growth, defects removal, grain boundary passivation and interactions at the CdS/CdTe interface during this CdCl2 heat treatment. As a result of this processing step, a drastic improvement in the device efficiency has been observed. However, the fine details of this processing step are not yet fully understood. More focussed research should be carried out in order to understand the fine details of these named areas.
This work shows that the CdCl2 treatment reduces a very broad mid-gap defects distribution to a comparatively narrow mid-gap defect level ~ 0.74 eV. The origin of these defects is not very clear, and these could be due to intrinsic defects or extrinsic defects due to inclusion of an unknown impurity into the crystal lattice. However, the PL work reported in ref.  for chemically etched CdTe surfaces indicates that these mid-gap defects level appears for Te-rich CdTe surfaces. This is helpful in drawing conclusions on mid-gap defects at ~ 0.74 eV that are mainly due to intrinsic defects. Since the surfaces are Te-rich, the possible native defects must be Cd-vacancies, Te-interstitials or Te-in Cd sites. Clearly, in order to remove this mid-gap defect level, CdTe should be grown with Cd-richness. According to the results reported in ref , mid-gap defects at ~ 0.74 eV are completely removed for Cd-rich CdTe surfaces. Therefore, without any doubt, high-efficiency CdTe solar cells will be produced when Cd-rich CdTe or n-type CdTe is used in CdS/CdTe solar cells.
2.1.4 Chloride treatment and positive contributions from grain boundaries
The literature also broadly reports the “grain boundary passivation” during CdCl2 treatment. This needs deep investigations and understanding. Our preliminary thoughts were published before , and following is the summary of our current understanding of positive contributions from grain boundaries for the PV activity.
With reference to the above discussion, it is now worth a comparison of two growth techniques: electrodeposition (ED) and close-space sublimation (CSS). ED is a low-temperature (< 100 °C) growth method, and CSS is a high-temperature (> 450 °C) growth technique. Therefore, the as-grown CdTe layers are very different; ED materials have grains in the nanoscale, and CSS materials have grown in µm scale. Therefore, the CdCl2 treatment for these two materials shows some differences. According to the above discussion, CdCl2 treatment provides two major changes: (i) formation of large crystals in the µm-scale covering the whole thickness of the film and (ii) the formation and/or enhancement of the transverse electric field (Et) across grain boundaries. During CdCl2 treatment of ED-CdTe, both these properties are introduced, and hence, the effect is drastic. However, in the case of CSS-CdTe, high-temperature grown materials have already formed large crystals in the µm-scale. Therefore, CdCl2 treatment introduces or enhances the value of Et showing a comparatively lower effect. But still there is a positive effect from the CdCl2 treatment.
2.1.5 Measurement of charge carrier mobility in CdTe thin films
The above discussion has been limited only to CdTe material and its solar cells. However, the observation of the large body of scientific publications on almost all polycrystalline PV materials shows columnar growth of these material layers. In particular, the low-temperature grown materials like CIGS, kesterites and perovskite materials show columnar growth and these columns extend throughout the device thickness. Therefore, the reported mobility values (µ׀׀) should be much lower than the real mobility values (µ┴) applicable when the device is operating. For the same reason, the theoretical calculations carried out with µ׀׀ should be revisited using more realistic µ┴ values. Hence, the theoretical predictions for device efficiencies are expected to increase.
2.2 Electrical contacts to CdTe
A comprehensive study on electrical contacts to II–VI compounds (CdTe, CdS, ZnSe) has been carried out by the main author of this article, focussing on CdTe bulk materials. All three possible surfaces: vacuum-cleaved, air-cleaved and chemically etched surfaces have been used for fabricating electrical contacts and studying their properties. Main findings have been published in several papers and summarised in a review article published in 1998 . Chemical etching is the relevant method for cleaning thin films and in thin film solar cell development. Therefore, it is appropriate to discuss the main features of these surfaces and electrical contacts fabricated on them.
2.2.1 Chemical etching of CdTe surfaces
Chemical etching of mechanically polished n-CdTe wafers clearly showed that the top layers can be easily modified by using chemical etchants. Acidic solutions preferentially remove Cd-element and leave a Te-rich surface. On the other hand, alkaline solutions preferentially remove Te-element and leave a Cd-rich surface. This chemical nature is identical for thin films of CdTe, and native oxides like TeO2 and CdTexOy compounds are also usually found on these chemically etched surfaces.
2.2.2 Fermi level pinning at n-CdTe/metal interfaces
The presence of high concentrations of defects at experimentally observed defect levels seriously affects the n-CdTe/metal contacts formed on chemically etched surfaces (see Figs. 5a and 6). A large number of metal contacts fabricated on these surfaces show the Fermi level pinning at one of these defect levels. Pinning position depends on the history of materials and the nature of the chemically etched surface. Te-rich n-CdTe surfaces tend to pin the FL at E1, E2 or E3 producing Schottky barriers (SB) with low-potential barrier heights (Ec–E1) ~ 0.40 (Ec–E2) ~ 0.65 or (Ec–E3) ~ 0.73 eV. Cd-rich n-CdTe surfaces show FL pinning at E4 or E5 yielding high-potential barrier heights (Ec–E4) ~ 0.96 or (Ec–E5) ~ 1.18 eV. When one of the defects has high concentrations, the SB formed is independent of the metal or the electrical contact material used. If the material used for the electrical contact induces drastic interface interactions, the barrier height could change due to the removal of FL pinning. In order to produce excellent rectifying contacts on n-CdTe surfaces, Cd-rich CdTe surfaces should be used with un-reactive metals or electrical contact materials (see Fig. 5c). This FL pinning possibility introduces reproducibility issues for n-CdTe/metal interfaces. In summary, if large SBs with excellent rectifying contacts are desired, the n-CdTe surface should be prepared with Cd-richness and a non-reactive material like Sb or any other conducting material should be used (see Ref. ).
2.3 Device architecture
In order to analyse and interpret electrical characteristics of CdS/CdTe hetero-junction-based devices, scientists must know the electrical conductivity of both materials without any ambiguity. The case for CdS is very clear due to its inherent n-type nature. But CdTe can exist in both n- and p-conduction types very easily. As shown in Sect. 2.1.1, the electrical conductivity can be changed simply by changing its composition or stoichiometry in ppm level. This is therefore highly applicable to any CdTe growth technique, and slight variation in growth parameters can change its electrical conductivity type. Always considering CdTe as a p-type material and interpreting the device results assuming an n-CdS/p-CdTe solar cell has been a serious issue in the past, and therefore, knowing the correct device architecture is essential in interpreting the experimental results and developing this device further.
2.3.1 p–n configuration
2.3.2 n–n + SB configuration
If the CdTe layer is grown as n-type in electrical conduction due to variation in growth conditions, then the CdS/CdTe hetero-junction is an n–n-type weak rectifying contact. During the fabrication of metal contacts to n-CdTe, the FL pinning effects described as in Fig. 6 apply. To form a device with the highest slope or an intense internal electric field, the FL should be pinned at E5 or forced to a place close to the VB maximum. In this situation, the device is an n–n + large SB at the back as shown in Fig. 7b. Now there are two rectifying interfaces: a weak rectifying junction at the n–n interface and a strong SB of ~ 1.18 eV at the back contact. These two junctions support each other adding currents, and therefore, the two junctions are connected in parallel. Since the SB is extremely large, even exceeding the potential barrier of CdTe p–n junction, and the whole device has a two-junction architecture, this device can perform better than the simple p–n junction. But unfortunately, optimisation of the device parameters by trial-and-error method, forming an n–n + SB device and then attempting to interpret the results using a simple p–n junction based on popular assumption, has been a real confusion in this field for several decades.
2.3.3 New experimental evidence for device architecture
The device architecture shown in Fig. 7b was first published in 2002  for high-performing CdS/CdTe solar cells, and the CdTe used in this device is reported as an n-type material. Soon after, in 2003, Jaegermann’s group reported  a surprising result of n-CdTe solar cells producing highest efficiencies. Their comprehensive work on surfaces and interfaces investigated the CdS/CdTe solar cell efficiency as a function of the position of the Fermi level in CdTe. They obtained highest efficiencies with n-type CdTe and reported “This surprising result does not correspond to the accepted model of the device physics of the CdS/CdTe solar cell,” i.e. the p–n junction model. More recently in 2013  and 2015 , comprehensive works on both theoretical and experimental work by NREL group reported that Cd-rich CdTe surfaces are more suitable for solar cell fabrication. Clearly, the Cd-rich CdTe material is n-type in electrical conduction, and therefore, the device architecture shown in Fig. 7b is more appropriate to describe the highest efficient CdS/CdTe solar cells.
2.4 High J sc values
Short circuit current density (Jsc) values of CdS/CdTe present another scientific controversy in this field. Shockley & Quiesser (S&Q) have calculated the possible efficiency limit for one-bandgap, p–n junction with CdTe . Loferski et al.  have also calculated the maximum Jsc values from one-bandgap CdTe p–n junction to be ~ 26 mA cm−2. In these calculations, only the photons with energy greater than the bandgap of CdTe have been considered for absorption and creation of e–h pairs. Although S&Q publication clearly stated that this value can be increased by including several bandgaps to absorb other low-energy photons, PV community has been adamant to accept any Jsc values greater than ~ 26 mA cm−2 for novel devices incorporating CdTe and other bandgap materials. The Jsc values can be increased well beyond the above value due to enhanced harvesting of photons using several other mechanisms.
If a device is designed and fabricated to absorb all photons in the solar spectrum, Jsc can be increased to achieve ~ 54 mA cm−2 . However, this cannot be achieved simply by adding consecutive material layers with smaller bandgaps, since the Voc depends on the smallest bandgap material used in the device. Therefore, other mechanisms should be introduced or activated in order to harvest low-energy photons and create more photo-generated charge carriers.
2.4.1 Impurity PV effect
In addition, the heat from the surrounding can also contribute to the multi-step absorption process providing another input of photons to this kind of devices. All these processes contribute to the increase in Jsc, when the right conditions exist in this type of devices. When the multi-step absorption process is dominant, the recombination process is suppressed in such devices.
2.4.2 Impact ionisation
In the type of devices shown in Fig. 9, the probability of impact ionisation also increases and takes place via two different mechanisms. The photo-generated electrons in the front of the device accelerate towards the back contact and travel through smaller bandgap materials. When the electron achieves kinetic energy greater than the bandgap of the absorbing material, an additional e–h pair is created by band-to-band transition (see Fig. 9).
The second type of impact ionisation is more attractive and highly possible. Towards the rear of the devices, native defects are filled by infrared (I-R) photons coming from both the solar spectrum and the surroundings. The accelerating photo-generated electrons from the front will have enough energy to transfer trapped electrons from defect levels to the conduction band. This combined process of impurity PV effect and impact ionisation has a high probability of creating more charge carriers, and this will be an avalanche effect. Since both impurity PV effect and impact ionisation are built into this device, and with an additional input from the surrounding I-R radiation, the Jsc can achieve very high values beyond ~ 26 mA cm−2 for CdTe solar cells. There are many publications with high Jsc values, and First Solar has also reported 31.69 mA cm−2 for CdS/CdTe solar cells  which is certainly exceeding 26 mA cm−2.
3 The way forward
3.1 Graded bandgap cells on p- and n-type windows
The main features of these devices are (i) presence of wide bandgap window material in the front, (ii) gradual reduction in the bandgap towards the back absorber material, (iii) slow change of electrical conductivity from p- to n- or n- to p-, and by keeping the smallest bandgap used at ~ 1.40 eV to achieve Voc values above 1.00 V, when optimised. The devices fabricated on p-windows are more attractive to achieve high performance.
Solar cells based on wide bandgap p-window materials have several advantages. (a) Potential barrier height created depends on the bandgap of the p-window material, and therefore, internal electric field created is high for separation of e–h pairs, and high Voc values are possible. (b) Photo-generated electrons in the front of the device accelerate across the device and see decreasing bandgaps towards the rear of the device increasing band-to-band impact ionisation. In both cases, Voc-limiting, smallest bandgap should be kept at ~ 1.40 eV to achieve Voc greater than 1.00 V.
3.2 Addition of ebdb and hbdb layers
Therefore, considering the prospects of thin film solar cells based on p-type window layer and inclusion of ebdb and hbdb layers, scientific community should further be focusing on implementing these ideas for CdTe-based devices and other thin film solar cells. Authors’ group has already conceptualised CdTe-based devices incorporating both of these ideas and aiming for further developments [65, 66].
4 Concluding remarks
The main controversy is the systematic determination of electronic conduction type of CdTe layers used in the highest efficiency CdS/CdTe solar cells instead of interpreting the outcomes relying on the popular assumption. Once the electronic conduction type is known, the relevant device architecture can be decided from the two possible situations, and then, the experimental results can be interpreted accurately and devices can be further developed according to solid-state physics principles.
Te-precipitation in CdTe material is an inherent property that can be detrimental for the device and should be resolved using relevant methods during growth and device processing steps. Further research on this matter is essential.
Charge carrier mobilities normal to the TCO layer (µ┴) should be measured instead of mobilities parallel to the TCO layer (µ׀׀). µ┴ could be much higher than µ׀׀ due to scattering from grain boundaries in the case of µ׀׀ and therefore could make a huge difference in the simulation work on this device.
In order to reduce the R&G process, the mid-gap defects in CdTe observed at ~ 0.74 eV should be minimised or completely removed. Extensive research attention is necessary in this front.
The highest efficiency devices reported to date have CdTe doping concentration in the range ~ (1013–1015) cm−3. Research should be directed to increase this to ~ (1015–1016) cm−3, in order to achieve better performance.
Next generation solar cells should be developed based on multilayer graded bandgap device structures. Therein, impurity PV effect and impact ionisation should be built into the same device to achieve the highest possible performance parameters.
Numerous researchers have contributed to this research programme over the last three decades. In particular, the main author would like to acknowledge the contributions from Chris Blomfield, Stephen McGregor, John McChesney, Anura Samanthilake, Nandu Chaure, Gavin Tolan, Gaafar Muftah, Jayne Wellings, Dahiru Diso, Osama El-Sherif, Ajith Weerasinghe, Fijay Fauzi, Azlian Abdul-Manaf, Mohammed Madugu, Olajide Olusola, Ruvini Dharmadasa, Thad Druffel, Gamini Sumanasekera, T. A. Krentsel and Jacek Jasinski. To enable this research, funding received from Sheffield Hallam University, EPSRC, British Council, Commonwealth Scholarship Commission, DTI-UK, University Alliance—UK, CARA and several Governments (Malaysian, Kurdistan, Libyan and Nigerian) are gratefully acknowledged.
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