Minimizing the TID effects due to gamma rays by using diamond layout for MOSFETs
- 18 Downloads
This manuscript describes an experimental comparative study of effects of the total ionizing dose (TID) on the main electrical parameters and figures of merit of Metal–Oxide–Semiconductor Field Effect Transistors (MOSFETs) implemented with two different layout styles, i.e., the hexagonal gate shape (diamond MOSFET, DM) and its corresponding rectangular counterparts (Conventional MOSFET, CM), which they were irradiated with a low dose rate with gamma-rays (60Co-source), considering that both present the same gate areas (AG), channel widths (W), aspect ratios (W/L), and concerning two different bias conditions (OFF and ON states) during the irradiation procedure. The main results of this work show that, besides the diamond MOSFETs present a better electrical performance than those found in their Conventional MOSFETs counterparts, they are also capable of boosting their ionizing radiation tolerances (smaller variation of the threshold voltage, subthreshold slope and minimize IDS leakage, etc.). Furthermore, it was observed that the hexagonal gate shape with a α angle equal to 90° tends to be the best gate geometry for MOSFETs because it is capable of enhancing the TID tolerance, intrinsically, in relation to the CM counterparts, regarding gamma-rays source used in this study. Therefore, the diamond layout style with α angle of 90° can be considered an alternative Hardness-By-Design layout technique which is able to manufacture planar MOSFETs low-cost, high electrical performance, and high ionizing tolerance to be applied in the space, medical, and nuclear CMOS ICs applications.
The authors would like to thank CNPq, FAPESP, CAPES and FINEP (CITAR) for the financial support and the Ionizing Radiation Laboratory (LRI) of the Institute of Advanced Studies (IEAv) for the infrastructure and test facilities. This study was supported by Financiadora de Estudos e Projetos (01.12.0224.00).
- 6.H.J. Barnaby, Modeling ionizing radiation effects in solid state materials and CMOS devices. IEEE Trans. Circ. Syst. 56(8), 1870–1883 (2009)Google Scholar
- 7.E.S.A. Handbook, Techniques for radiation effects mitigation in ASICs and FPGAs. ESA ESTEC. Data systems division microelectronics. Section Noordwijk, Netherlands, (2016). http://microelectronics.esa.int/asic/ECSS-Q-HB-60-02A1September2016.pdf. Accessed 1 Sept 2016
- 10.J. Jiang, W. Shu, K.-S. Chong, Total Ionizing Dose (TID) effects on finger transistors in a 65 nm CMOS process. In: 2016 IEEE international symposium on circuits and systems (ISCAS), p. 5–8, Montreal, Canada; (2016)Google Scholar
- 11.J. Ramos-Martos et al., Radiation characterization of the Austria-microsystems 0.35 m CMOS technology. In: 2011 12th European conference on radiation and its effects on components and systems, Sevilla, Spain; (2011)Google Scholar
- 12.V. Ferlet, Design hardening methodologies for ASICs, in radiation effects on embedded systems (Springer, Dordrecht, 2007)Google Scholar
- 19.M. Mclain et al., Modeling dogbone gate geometry n-channel MOSFETs. In: 8th European conference on radiation and its effects on components and systems, RADECS 2005. Cap d’Agde, France; (2005)Google Scholar
- 21.S.P. Gimenez, R.D. Leoni, C. Renaux, D. Flandre, Using the diamond layout style to boost MOSFET frequency response of analog IC. Electron. Lett. 50, 398–400 (2014)Google Scholar
- 24.S.P. Gimenez, Layout Techniques for MOSFETs. Synthesis Lectures on Emerging Engineering Technologies, vol. 2, no. 6 (Morgan & Claypool, 2016), pp. 1–81. https://doi.org/10.2200/S00704ED1V01Y201602EET007
- 29.O.L. Gonçalez et al, Qualification of electronic components with respect to the cosmic radiation tolerance for space applications. An. WERICE, 2012. São José dos Campos, 1, 51–56 (2012). http://www.ieav.cta.br/werice2012/Anais%20werice.pdf. Accessed 5 May 2018
- 30.MOSIS, ON Semiconductor 0.35 Micron. https://www.mosis.com/vendors/view/on-semiconductor/i3t50 (2017)
- 31.R.D. Schrimpf, R. Velazco, Radiation effects in microelectronics, in Radiation Effects on Embedded Systems (Holland, Springer, 2007), pp. 11–29Google Scholar
- 33.D. Lili et al, Study of radiation-induced leakage current between adjacent devices in a CMOS integrated circuit. J Semicond. NS-6 33, 1–6 (2012)Google Scholar