Electrical characteristics of Si-nanoparticle/Si-nanowire-based field-effect transistors
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In this study, Si-nanoparticle(NP)/Si-nanowire(NW)-based field-effect transistors (FETs) with a top-gate geometry were fabricated and characterized. In these FETs, Si NPs were embedded as localized trap sites in Al2O3 top-gate layers coated on Si NW channels. Drain current versus drain voltage (IDS−VDS) and drain current versus gate voltage (IDS−VGS) were measured for the Si NP/Si NW-based FETs to investigate their electrical and memory characteristics. The Si NW channels were depleted at VGS = 9 V, indicating that the devices functioned as p-type depletion-mode FETs. The top-gate Si NW-based FETs decorated with Si NPs show counterclockwise hysteresis loops in the IDS−VGS curves, revealing their significant charge storage effect.
KeywordsHigh Resolution Transmission Electron Microscopy High Resolution Transmission Electron Microscopy Atomic Layer Deposition Drain Voltage Al2O3 Layer
This work was supported by the Center for Integrated-Nano-Systems (CINS) of the Korea Research Foundation (KRF-2006-005-J03601), the Korea Science and Engineering Foundation (KOSEF) through the National Research Lab. Program (R0A-2005-000-10045-02 (2007)), the Nano R&D Program (M10703000980-07M0300-98010), and “SystemIC2010” project of Korea Ministry of Commerce, Industry and Energy.
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