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Journal of Intelligent Manufacturing

, Volume 22, Issue 3, pp 399–412 | Cite as

UNISON analysis to model and reduce step-and-scan overlay errors for semiconductor manufacturing

  • Chen-Fu Chien
  • Chia-Yu Hsu
Article

Abstract

Semiconductor industry has been one of the most complicated industries driven by Moore’s Law for continuous technology evolution. In order to meet the requirements of high resolution and alignment accuracy, the lithography equipments have been advanced from step-and-repeat system to step-and-scan system. As the tolerance of linewidths is becoming tight and slight, overlay errors must be controlled within the tolerance to maintain the yield. In particular, overlay errors can be compensated by modifying the corresponding equipment setup parameters. However, little research has been done to deal with overlay errors of the step-and-scan system. This study aimed to develop a modeling and decision analysis framework in which the overlay error model for step-and-scan system was constructed and the optimal sampling strategy for measuring and compensating the overlay errors was thus designed. Furthermore, we validated the proposed model and sampling strategy by empirical studies conducted in a fab. We compared the proposed sampling strategy with alternative sampling strategies including the existing sampling strateg based on the model adequacy of R-squares and the model effectiveness of residual errors. The results demonstrated the practical viability of the proposed approach.

Keywords

Modeling and analysis for semiconductor manufacturing Overlay Sampling strategy Design of experiment Intelligent manufacturing 

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References

  1. Buckley J. D., Karatzas C. (1989) Step and scan: A system overview of a new lithography tool. Proceedings of SPIE: Optical/Laser Microlithography II 1088: 424–433Google Scholar
  2. Chien C.-F., Chang K.-H., Chen C.-P. (2003) Design of a sampling strategy for measuring and compensating for overlay errors in semiconductor manufacturing. International Journal of Production Research 41(11): 2547–2561CrossRefGoogle Scholar
  3. Chien C.-F., Hsu C.-Y. (2006) A novel method for determining machine subgroups and backups with an empirical study for semiconductor manufacturing. Journal of Intelligent Manufacturing 17(4): 429–440CrossRefGoogle Scholar
  4. Chien C.-F., Wang H.-J., Wang M. (2007) A UNISON framework for analyzing alternative strategies of IC final testing for enhancing overall operational effectiveness. International Journal of Production Economics 107(1): 20–30CrossRefGoogle Scholar
  5. Chien C.-F., Wu J.-Z. (2003) Analyzing repair decisions in the site imbalance problem of semiconductor test machines. IEEE Transactions on Semiconductor Manufacturing 16(4): 704–711CrossRefGoogle Scholar
  6. Cronin D. J., Gallatin G. M. (1994) Micrascan II overlay error analysis. Proceedings of SPIE: Optical/Laser Microlithography VII 2197: 932–942Google Scholar
  7. Fink D., Sullivan N. T., Lekas J. S. (1994) Overlay sample plan optimization for the detection of higher order contributions to misalignment. Proceedings of SPIE: Integrated Circuit Metrology, Inspection, and Process Control VIII 2196: 389–399Google Scholar
  8. Hong J., Lee J., Park J., Cho H., Moon J. (1999) Optimization of sample plan for overlay and alignment accuracy improvement. Japanese Journal of Applied Physics 38: 7164–7167CrossRefGoogle Scholar
  9. Leachman R., Ding S., Chien C.-F. (2007) Economic efficiency analysis of wafer fabrication. IEEE Transactions on Automation Science and Engineering 4(4): 501–512CrossRefGoogle Scholar
  10. Levinson H. J., Preil M. E., Lord P. J. (1997) Minimization of total overlay errors on product wafers using an advanced optimization scheme. Proceedings of SPIE: Optical Microlithography X 3051: 362–373Google Scholar
  11. Lin Z.-C., Wu W.-J. (1999) Multiple linear regression analysis of the overlay accuracy model. IEEE Transaction on Semiconductor Manufacturing 12(2): 229–237CrossRefGoogle Scholar
  12. MacMillen D., Ryden W. D. (1982) Analysis of image field placement deviations of a 5 × microlithographic reduction lens. Proceedings of SPIE: Optical Microlithography-Technology 334: 78–89Google Scholar
  13. Montgomery D. C. (2001) Design and analysis of experiments. Wiley, New YorkGoogle Scholar
  14. Pellegrini J. C., Hatab Z. R., Brsh M., Glass T. R. (1999) Super sparse overlay sampling plans: An evaluation of methods and algorithms for optimizing overlay quality control and metrology tool throughput. Proceedings of SPIE: Metrology, Inspection, and Process Control for Microlithography XIII 3677: 72–82Google Scholar
  15. Rangarajan B., Templeton M., Capodieci L., Subramanian R., Scranton A. (1998) Optimal sampling strategies for sub-100 nm overlay. Proceedings of SPIE: Metrology, Inspection, and Process Control for Microlithography XII 3332: 348–359Google Scholar
  16. Schoot J. V., Bornebroek F., Suddendorf M., Mulder M., van der Spek J., Stoeten J., Hunter A. (1999) 0.7 NA DUV step & scan system for 150 nm imaging with improved overlay. Proceedings of SPIE: Optical Microlithography XII 3679: 448–463Google Scholar
  17. Sewell H. (1994) Step and scan: The maturing technology. Proceedings SPIE: Optical/Laser Microlithography VIII 2440: 49–60Google Scholar
  18. van den Brink M. A., de Mol C. G. M., George R. A. (1988) Matching performance for multiple wafer steppers using an advanced metrology procedure. Proceedings SPIE: Integrated Circuit Metrology, Inspection, and Process Control II 921: 180–197Google Scholar
  19. van den Brink M., Jasper H., Slonaker S., Wijnhoven P., Klaassen F. (1996) Step-and-scan and step-and-repeat: A technology comparison. Proceedings of SPIE: Optical Microlithography IX 2726: 734–753Google Scholar
  20. Wu J.-Z., Chien C.-F. (2008) Modeling strategic semiconductor assembly outsourcing decisions based on empirical settings. OR Spectrum 30(3): 401–430CrossRefGoogle Scholar
  21. Zwart G., van den Brink M., George R., Satriasaputra D., Baselmans J., Butler H., van Schoot J., de Klerk J. (1997) Performance of a step and scan system for DUV lithography. Proceedings of SPIE: Optical Microlithography X 3051: 817–829Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.Department of Industrial Engineering and Engineering ManagementNational Tsing Hua UniversityHsinchuTaiwan

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