Advertisement

Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations

  • Ayan PalchaudhuriEmail author
  • Anindya Sundar Dhar
Article
  • 40 Downloads

Abstract

Canonic signed digit (CSD) recoding finds applications in real time VLSI signal processing. In this paper, we have proposed optimized FPGA implementations of CSD recoding techniques starting from a two’s complement input and a redundant signed digit (SD) input. The architectures exploit the fast, hardwired fabric resources of the FPGA logic elements to give rise to a circuit realization optimized for speed and area. The underutilized logic elements configuring the original design are further targeted to append suitable fault localization circuitry without any compromise in speed and area. This makes the designs attractive for implementation in an era where reliability issues of semiconductor chips are on the rise owing to extensive miniaturization of physical device dimensions. Primitive instantiation and constrained placement based design approach allow us to conveniently select the logic area for mapping or to detect and bypass any physical FPGA slice coordinates if deemed faulty.

Keywords

Canonic signed digit Redundant signed digit FPGA Fault localization C-testability Monitor signals Alternating logic 

Notes

References

  1. 1.
    Parhi KK (2007) VLSI digital signal processing systems: design and implementation. Wiley India Pvt. LimitedGoogle Scholar
  2. 2.
    Faust M, Gustafsson O, Chang CH (2011) Fast and VLSI efficient binary-to-CSD encoder using bypass signal. Electron Lett 47(1):18–20CrossRefGoogle Scholar
  3. 3.
    Ruiz GA, Granda M (2011) Efficient canonic signed digit recoding. Microelectron J 42(9):1090–1097CrossRefGoogle Scholar
  4. 4.
    Herrfeld A, Hentschke S (1995) Look-ahead circuit for CSD-code carry determination. Electron Lett 31 (6):434–435CrossRefGoogle Scholar
  5. 5.
    Koç KÇ (1996) Parallel canonical recoding. Electron Lett 32(22):2063–2065CrossRefGoogle Scholar
  6. 6.
    He Y, Zhang Z, Ma B, Li J, Zhen S, Luo P, Li Q (2015) A fast and energy efficient binary-topseudo CSD converter. In: Proc. IEEE international symposium on circuits and systems (ISCAS), pp 838–841Google Scholar
  7. 7.
    Tanaka Y (2016) Efficient signed-digit-to-canonical-signed-digit recoding circuits. Microelectron J 57:21–25CrossRefGoogle Scholar
  8. 8.
    Palchaudhuri A, Dhar AS (2018) High speed FPGA fabric aware CSD recoding with run-time support for fault localization. In: Proc. 31st international conference on VLSI design (VLSID), pp 186–191Google Scholar
  9. 9.
    Palchaudhuri A, Dhar AS (2017) Built-in fault localization circuitry for high performance FPGA based implementations. J Electron Test 33(4):529–537CrossRefGoogle Scholar
  10. 10.
    Naouss M, Marc F (2016) Modelling delay degradation due to NBTI in FPGA look-up tables. In: Proc. 26th international conference on field programmable logic and applications (FPL), pp 1–4Google Scholar
  11. 11.
    Naouss M, Marc F (2016) FPGA LUT delay degradation due to HCI: experiment and simulation result. Microelectron Reliab 64:31–35CrossRefGoogle Scholar
  12. 12.
    Palchaudhuri A, Dhar AS (2017) Redundant arithmetic based high speed carry free hybrid adders with built-in scan chain on FPGAs. In: Proc. 24th IEEE international conference on high performance computing (HiPC), pp 104–113Google Scholar
  13. 13.
    Basha BC, Pillement S, Piestrak SJ (2015) Fault-aware configurable logic block for reliable reconfigurable FPGAs. In: Proc. IEEE international symposium on circuits and systems, pp 2732–2735Google Scholar
  14. 14.
    Rao PMB, Amouri A, Kiamehr S, Tahoori MB (2013) Altering LUT configuration for wear-out mitigation of FPGA-mapped designs. In: Proc. 23rd international conference on field programmable logic and applications, pp 1–8Google Scholar
  15. 15.
    Raik J, Rannaste A, Jenihhin M, Villukas T, Ubar R, Fujiwara H (2011) Constraint-based hierarchical untestability identification for synchronous sequential circuits. In: Proc. 16th IEEE european test symposium (ETS), pp 147–152Google Scholar
  16. 16.
    Raik J, Ubar R, Krivenko A, Kruus M (2007) Hierarchical identification of untestable faults in sequential circuits. In: Proc. 10th euromicro conference on digital system design architectures, methods and tools (DSD), pp 668–671Google Scholar
  17. 17.
    Raik J, Fujiwara H, Ubar R, Krivenko A (2008) Untestable fault identification in sequential circuits using model-checking. In: Proc. 17th asian test symposium (ATS), pp 21–26Google Scholar
  18. 18.
    Bernardeschi C, Cassano L, Domenici A, Sterpone L (2016) Ua 2TPG: an untestability analyzer and test pattern generator for SEUsin the configuration memory of SRAM-based FPGAs. Integration the VLSI Journal 55:85–97CrossRefGoogle Scholar
  19. 19.
    Bernardeschi C, Cassano L, Domenici A, Sterpone L (2013) Unexcitability analysis of SEUs affecting the routing structure of SRAM-based FPGAs. In: Proc. 23rd ACM international conference on great lakes symposium on VLSI (GLSVLSI), pp 7–12Google Scholar
  20. 20.
    Bernardeschi C, Cassano L, Domenici A, Sterpone L (2012) SEU-X: a SEU un-excitability prover for SRAM-FPGAs. In: Proc. 18th IEEE international on-line testing symposium (IOLTS), pp 25–30Google Scholar
  21. 21.
    Tiwari A, Tomko KA (2003) Scan-chain based watch-points for efficient run-time debugging and verification of FPGA designs. In: Proc. 8th Asia and South Pacific design automation conference (ASP-DAC), pp 705–711Google Scholar
  22. 22.
    Gupte A, Vyas S, Jones PH (2015) A fault-aware toolchain approach for FPGA fault tolerance. ACM Trans Design Automation Electron Syst 20(2):32:1—32:22Google Scholar
  23. 23.
    Modi H, Athanas P (2015) In-system testing of Xilinx 7-series FPGAs: part 1-logic. In: Proc. IEEE international conference for military communications, pp 477–482Google Scholar
  24. 24.
    Devlin BS, Camarota RC (2017) Circuit for and method of implementing a scan chain in programmable resources of an integrated circuit. United States Patent Application Publication Patent 20 170 373 692Google Scholar
  25. 25.
    Palchaudhuri A, Amresh AA, Dhar AS (2017) Efficient automated implementation of testable cellular automata based pseudorandom generator circuits on FPGAs. J Cell Autom 12(3–4):217–247MathSciNetGoogle Scholar
  26. 26.
    Nazar GL, Carro L (2012) Fast error detection through efficient use of hardwired resources in FPGAs. In: Proc. 17th IEEE European test symposium, pp 1–6Google Scholar
  27. 27.
    Kyriakoulakos K, Pnevmatikatos D (2009) A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support. In: Proc. 19th international conference on field programmable logic and applications, pp 193–198Google Scholar
  28. 28.
    Palchaudhuri A, Dhar AS (2016) Efficient implementation of scan register insertion on integer arithmetic cores for FPGAs. In: Proc. 29th international conference on VLSI design, pp 433–438Google Scholar
  29. 29.
    Lala PK, Burress AL (2003) Self-checking logic design for FPGA implementation. IEEE Trans Instrum Meas 52(5):1391–1398CrossRefGoogle Scholar
  30. 30.
    Palchaudhuri A, Dhar AS (2019) Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies. J Parallel Distributed Comput 130:110–125CrossRefGoogle Scholar
  31. 31.
    Ehliar A (2010) Optimizing Xilinx designs through primitive instantiation. In: Proc. 7th FPGAworld conference, pp 20–27Google Scholar
  32. 32.
    Palchaudhuri A, Chakraborty RS (2016) High performance integer arithmetic circuit design on FPGA: architecture, implementation and design automation. Springer, IndiaGoogle Scholar
  33. 33.
    Xilinx Inc. (2016) 7 series FPGAs configurable logic block user guide UG474 (v1.8). [Online]. Available: https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
  34. 34.
    Verma AK, Brisk P, Ienne P (2009) Challenges in automatic optimization of arithmetic circuits. In: Proc. 19th IEEE symposium on computer arithmetic, pp 213–218Google Scholar
  35. 35.
    Kumm M, Abbas S, Zipf P (2015) An efficient softcore multiplier architecture for Xilinx FPGAs. In: Proc. 22nd IEEE symposium on computer arithmetic, pp 18–25Google Scholar
  36. 36.
    Kumm M, Kleinlein M, Zipf P (2016) Efficient sum of absolute difference computation on FPGAs. In: Proc. 26th international Conference on Field Programmable Logic and Applications (FPL), pp 1–4Google Scholar
  37. 37.
    Palchaudhuri A, Dhar AS (2019) VLSI architectures for Jacobi symbol computation. In: Proc. 32nd international conference on VLSI design, pp 335–340Google Scholar
  38. 38.
    Zicari P, Perri S (2010) A fast carry chain adder for Virtex-5 FPGAs. In: Proc. 15th IEEE mediterranean electrotechnical conference (MELECON), pp 304–308Google Scholar
  39. 39.
    Palchaudhuri A, Dhar AS (2016) High performance bit-sliced pipelined comparator tree for FPGAs. In: Proc. 20th international symposium on VLSI design and test (VDAT), pp 1–6Google Scholar
  40. 40.
    Källström P, Gustafsson O (2016) Fast and area efficient adder for wide data in recent Xilinx FPGAs. In: Proc. 26th international conference on field programmable logic and applications (FPL), pp 1–4Google Scholar
  41. 41.
    Palchaudhuri A, Dhar AS (2018) Fast carry chain based architectures for two’s complement to CSD recoding on FPGAs. In: Proc. 14th international symposium on applied reconfigurable computing (ARC), pp 537–550CrossRefGoogle Scholar
  42. 42.
    Ye SM, Laih CS, Chen CH, Lee JY (1992) An efficient redundant-binary number to binary number converter. IEEE Journal of Solid-State Circuits 27(1):109–112CrossRefGoogle Scholar
  43. 43.
    Herrfeld A, Hentschke S (1995) Conversion of redundant binary into two’s complement representations. Electron Lett 31(14):1132–1133CrossRefGoogle Scholar
  44. 44.
    Wang G, Tull MP (2004) A new redundant binary number to 2’s-complement number converter. In: Proc. region 5 conference: annual technical and leadership workshop, pp 141–143Google Scholar
  45. 45.
    He Y, Chang CH (2008) A Power-Delay efficient hybrid carry-lookahead/carry-select based redundant binary to two’s complement converter. IEEE Trans on Circ Sys I 55(1):336–346MathSciNetGoogle Scholar
  46. 46.
    Sahoo SK, Gupta A, Asati AR, Shekhar C (2010) A novel redundant binary number to natural binary number converter. J Signal Process Sys 59(3):297–307CrossRefGoogle Scholar
  47. 47.
    Barik RK, Pradhan M, Panda R (2017) Efficient conversion technique from redundant binary to nonredundant binary representation. J Circ Sys Comput 26(9):1–8Google Scholar
  48. 48.
    Palchaudhuri A, Dhar AS (2018) Redundant binary to two’s complement converter on FPGAs through fabric aware scan based encoding approach for fault localization support. In: Proc. IEEE international parallel and distributed processing symposium (IPDPS) workshops, pp 218–221Google Scholar
  49. 49.
    Saposhnikov VV, Saposhnikov VV, Dmitriev A, Goessel M (1998) Self-dual duplication for error detection. In: Proc. seventh asian test symposium, pp 296–300Google Scholar
  50. 50.
    Friedman AD (1994) A functional approach to efficient fault detection in iterative logic arrays. IEEE Transcations on Computers 43(12):1365–1375CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Electrical Communication EngineeringIndian Institute of Technology KharagpurKharagpurIndia

Personalised recommendations